October 13th, Noon – 3:30pm (in-person) – San Jose Convention Center, Lower Level, Room LL21BVirtual content
The P4 Workshop event is an opportunity for the P4 ecosystem to share knowledge, insights and experiences across the broader community and to facilitate collaboration. This year the workshop will be a hybrid event and feature both in-person and pre-recorded content. The in-person portion of the workshop will take place on October 13th in conjunction with the 2025 OCP Global Summit at the San Jose Convention Center in San Jose, California.
Registration for the P4 Workshop is included as part of OCP Global Summit registration – no additional fees are required – Register Now!
In addition, a P4 booth will be in the OCP Global Summit exhibit hall – make sure and stop by to talk with community members and learn about P4, how its used and how to participate. Don’t miss a demo – “Gigaflow: Pipeline-Aware Caching in Virtual Switches with P4”.
P4 Workshop Agenda (October 13th – noon – 3:30pm)
- Welcome – Fernando Ramos
General Chair 2025 P4 Workshop
- KEYNOTE: Mina Tahmasbi Arashloo – “High-Level and Target-Agnostic Transport Programs”
Assistant Professor Canada Research Chair in Minimizing Human Error in Modern Networks Cheriton School of Computer Science, University of Waterloo
Abstract: Over the past two decades, programming abstractios for packet processing have gained widespread adoption. These abstractions enable network operators to specify packet processing logic in high-level, domain-specific languages that are independent of the underlying hardware architecture of packet processing nodes. This approach has unlocked numerous benefits, including compiler-driven generation of efficient low-level implementations, portability across diverse execution environments, and automated testing and verification. Most existing abstractions, however, primarily focus on L2/L3 packet processing. In this talk, we highlight the need for new programming abstractions that capture the complexities of network mechanisms essential for quality of service, specifically transport protocols.
- Victor Rios – “DVaaS Detective: The Case of the Failing Tests”
Software Engineer, Google
- Anand Sridharan – “Cisco Silicon One: Unifying Network Forwarding with P4 Program”
Distinguished Engineer, Cisco
BREAK
- Tom Herbert – “Unifying P4 with eBPF and DPDK via XDP2”
CEO, XDPnet
- Debashis Chatterjee – “New Dawn of P4”
Senior Director of Engineering, Intel
- Fabian Ruffy | Vladimir Gurevich – “XASM: A Foundation to Program the X2 with P4”
Software Architect | Customer Solutions Architect, XSight Labs
- KEYNOTE: Krishna Doddapaneni – “Using P4 NICs for resilient scale-out GPU interconnect”
Corporate Vice President, AMD Pensando
Abstract: AI transports demand hardware-based solution for low latency, high throughput GPU interconnects. P4 seems a perfect match for demanding datapath transport enabled on programmable NIC for scale-out Ethernet fabrics. The industry is standardizing packet processing, memory transfers, message processing, reliability, multipathing, etc. over the last few years. And we are at the beginning of building and standardizing these solutions. As network components multiplies — from cables and NICs to switches and transceivers, failures become an inevitability. Chasing a myth of perfect reliability, a more practical approach is to design a programmable network that anticipates and handles these failures gracefully.
This talk discusses how AMD leverages the P4 to build a robust solution that overcomes network failures, implementing a multi-plane architecture and advanced failure-handling mechanisms. How P4 capabilities demonstrate network data plane programmability is a foundational requirement in today’s demanding and unforgiving AI environments.
- Andy Fingerhut – P4 Workshop Wrap-up
Principal Engineer, Cisco
P4 Workshop Pre-Recorded Talks
- Eric Campbell – “When P4 Isn’t Enough: Specifying The Control Interface”
Postdoctoral Research Fellow, UT Austin
- Mehmet Emin Sahin – “High-Accuracy Updatable Bloom Filters for Robust Network Security in Programmable Networks”
Systems and Network Administrator, The Scientific and Technological Research Council of Turkiye
- Mirek Walukiewicz – “Virtual IP Load Balancer using P4”
Principal Engineer, Altera
- Phani Suresh Paladugu – “Enabling Programmable Performance: Memory and Interconnect Innovation for AI-Centric Data Planes”
Executive Director – Product Management, Synopsys
- Jitesh Sreedharan Nambiar – “AI‑Enabled BOM Lifecycle for P4‑Programmable Infrastructure Reliability”
BE Graduate, Mumbai University
- Mohammad Firas Sada – “Cross-Federated P4 Research Testbed for Wide-Area Programmable Networking Experiments”
Data Science Research Specialist, San Diego Supercomputer Center
- Shaan Nagy | Ali Kheradmand – “Automated Switch Validation with Path-Complete Testing at Scale”
PhD Student, UCSD | Senior Software Engineer, Google
- Amith Gspn – “Real-Time Encrypted Traffic Classification with P4 and DPDK”
Graduate Student Assistant and PhD Student, University of South Carolina
P4 Demo
Advay Singh | Ali Imran | Muhammad Shahbaz – “Gigaflow: Pipeline-Aware Caching in Virtual Switches with P4”
Research Assistant | Graduate Student Research Assistant | Assistant Professor EECS – Computer Science and Engineering, University of Michigan
General Chair
Fernando Ramos, University of Lisbon
Program Committee
Amedeo Sapio, NVIDIA
Andy Fingerhut, Cisco
Ben Pfaff, Feldera
Chris Sommers, KeySight
Gianni Antichi, Politecnico di Milano & Queen Mary University of London
Jonathan DiLorenzo, Google
Mario Baldi, NVIDIA
Muhammad Shahbaz, University of Michigan
Vladimir Gurevich, P4ica
All attendees and participants are expected to behave in accordance with professional standards and the Linux Foundation Events Code of Conduct – for more information, see the full Code here.
