P4 Developer Days is a series of live educational webinar recordings featuring different P4-related topics and presented by members of the P4 community. If you are interested in proposing a topic to present at an upcoming P4 Developer Day, please email a short abstract of your proposed topic to andy.fingerhut@gmail.com
Elie Kfoury received the Ph.D. degree in Informatics from the University of South Carolina (USC), in 2023. He is currently an assistant professor in the Integrated Information Technology department at USC. As a member of the Cyberinfrastructure Laboratory, he developed training materials using virtual labs on high-speed networks, TCP congestion control, programmable switches, SDN, and cybersecurity. His research interests include P4 programmable data planes, cybersecurity, and Blockchain. He previously worked as a research and teaching assistant in the computer science department at the American University of Science and Technology in Beirut.
Jorge Crichigno received the Ph.D. degree in computer engineering from The University of New Mexico, Albuquerque, USA, in 2009. He is a Professor with the College of Engineering and Computing, University of South Carolina (USC), and the Director of the Cyberinfrastructure Laboratory, USC. His work has been funded by private industry and U.S. agencies such as the National Science Foundation (NSF), the Department of Energy, and the Office of Naval Research (ONR). He has over 15 years of experience in the academic and industry sectors. His research interests include P4 programmable switches, implementation of high-speed networks, network security, TCP optimization, offloading functionality to programmable switches, and IoT devices
A key barrier to the faster adoption of programmable data planes (e.g., P4 switches, SmartNICs, end-hosts) is the lack of engaging training materials. This NSF Cybertraining project aims to address this challenge by developing hands-on virtual labs (vLabs) for online instruction. These vLabs will be deployed on FABRIC, an NSF-funded international infrastructure for research at scale, and on the Academic Cloud, a training and research cloud system maintained by the University of South Carolina.
The team has already created approximately 30 vLabs on BMv2, the P4 software switch. The project will now focus on open-source technologies related to SmartNICs and end-host stacks (e.g., PNA, P4-DPDK, P4TC, P4-eBPF, etc.). The developed vLabs will be open-source and available to the community. Learners will be provided with detailed laboratory manuals and access to the training platforms, which are accessible from the Internet using a regular web browser (no SSH or installations required).
Steffen Lindner is a postdoctoral researcher specialized in software-defined networking (SDN), P4, Time-Sensitive Networking (TSN), and congestion management. He studied, worked, and obtained his bachelor’s (2017), master’s (2019), and Ph.D. (2024) degrees at the University of Tuebingen.
We present P4TG, an open-source P4-based traffic generator (TG) which runs on the programmable Intel Tofino ASIC. In generation mode, P4TG is capable of generating traffic up to 1 Tb/s split across 10x 100 Gb/s ports. Thereby it measures rates directly in the data plane. Generated traffic may be fed back from the output to the input ports, possibly through other equipment, to record packet loss, packet reordering, inter-arrival times (IATs) and sampled round trip times (RTTs). Further, it supports VLAN, QinQ, and MPLS encapsulation. In analysis mode, P4TG measures rates on the input ports and IATs, and forwards traffic through its output ports. Existing software or P4-based traffic generators either lack the required accuracy, do not support high data rates, or do not provide sufficiently integrated measurement capabilities.
Ryan Goodfellow is a networking engineer at Oxide Computer Company. He works in a small team that has built the networking foundation for a rack-scale computer from the ground up with P4 at the core. Building a computing platform around P4 has provided an in-depth understanding of the P4 language and a breadth of experience in the technical machinery and ecosystem that must exist around the language to innovate successfully with P4. Ryan’s current work in P4 is centered around the idea that for a language ecosystem to thrive, the challenges at the hardware-software interface must be open to the engineering teams building systems on the language. To this end, he’s been working on an open ISA for P4 to allow for full-stack open-source compilers to be created.
At Oxide, we’re big proponents of both open-source and programmable networking. In this talk, I’ll present our P4 compiler x4c, and how we leverage the flexibility it provides us to build a product with P4 at the core while still maintaining test and CI-driven workflows. One of the primary challenges of building a product around P4 is integrating P4-programmable elements into a broader hardware/software system and testing at the scale and complexity the system is designed to operate at in a virtualized setting, as doing so physically is not economically feasible.
Fabrian Ruffy is a PhD candidate in the systems lab at New York University, a part-time research assistant at Intel, and a member of the P4 Technical Steering Team (TST). He works with Anirudh Sivaraman on problems related to data center networking, more specifically programmable networks. Previously, he was a Master’s student in the Networks, Systems, and Security lab of the University of British Columbia, where he was advised by Ivan Beschastnikh.
We present P4Testgen, a test oracle for the P4-16 language that supports automatic generation of packet tests for any P4-programmable device. Given a P4 program and sufficient time, P4Testgen generates tests that cover every reachable statement in the input program. Each generated test consists of an input packet, control-plane configuration, and output packet(s), and can be executed in software or on hardware. Unlike prior work, P4Testgen is open source and extensible, making it a general resource for the community. P4Testgen not only covers the full P4-16 language specification, it also supports modeling the semantics of an entire packet-processing pipeline, including target-specific behaviors-i.e., whole-program semantics. Handling aspects of packet processing that lie outside of the official specification is critical for supporting real-world targets (e.g., switches, NICs, end host stacks). In addition, P4Testgen uses taint tracking and concolic execution to model complex externs (e.g., checksums and hash functions) that have been omitted by other tools, and ensures the generated tests are correct and deterministic. We have instantiated P4Testgen to build test oracles for the V1model, eBPF, and the Tofino (TNA and T2NA) architectures; each of these extensions only required effort commensurate with the complexity of the target. We validated the tests generated by P4Testgen by running them across the entire P4C program test suite as well as the Tofino programs supplied with Intel’s P4 Studio. In just a few months using the tool, we discovered and confirmed 25 bugs in the mature, production toolchains for BMv2 and Tofino, and are conducting ongoing investigations into further faults uncovered by P4Testgen.
Please see github
Mihai Budiu is a research at VMware Research. He holds a holds a Computer Science, Ph.D, from Carnegie Mellon University and after graduate school was a researcher at Microsoft Research in Silicon Valley for 10 years. When the Microsoft lab was dismantled, in the fall of 2014, he joined Barefoot Networks. His role was to help design and implement a new version of the P4 language, which became later known as P4-16. He initiated (with Chriss Dodd) the development of the open source P4-16 compiler infrastructure. After Barefoot he joined VMware Research. At VMware he has continued to support the P4 language as a core contributor to the open-source compiler and later as a co-chair of the P4 Language Design Working Group.
Mihai Budiu is a research at VMware Research. He holds a holds a Computer Science, Ph.D, from Carnegie Mellon University and after graduate school was a researcher at Microsoft Research in Silicon Valley for 10 years. When the Microsoft lab was dismantled, in the fall of 2014, he joined Barefoot Networks. His role was to help design and implement a new version of the P4 language, which became later known as P4-16. He initiated (with Chriss Dodd) the development of the open source P4-16 compiler infrastructure. After Barefoot he joined VMware Research. At VMware he has continued to support the P4 language as a core contributor to the open-source compiler and later as a co-chair of the P4 Language Design Working Group.
