P4 Developer Days – Implementation of Periodic Behavior with P4: Challenges and Solutions on Intel Tofino with Application in Time-Sensitive Networking (TSN)

Register to attend this P4 Developer Days webinar, “Implementation of Periodic Behavior with P4: Challenges and Solutions on Intel Tofino with Application in Time-Sensitive Networking (TSN)”

Date: November 19, 2025
Time: 8:00am Pacific

Abstract

Implementing periodic time behavior in hardware data planes is challenging due to limited arithmetic capabilities such as the lack of modulo operations, restricted timestamp precision, and resource constraints. This talk presents a general mechanism for implementing periodic time logic in P4, i.e., enabling data plane behavior that repeats in fixed time intervals, applicable to a broad range of time-aware applications. The mechanism enables periodic packet matching by mapping absolute timestamps to relative positions within a hyperperiod. To emulate hyperperiod boundaries, we leverage the switch’s internal packet generator to generate periodic trigger packets that act as time anchors for computing relative timestamps.

As a concrete use case, we apply this mechanism to implement Per-Stream Filtering and Policing (PSFP) as defined in IEEE 802.1Qci. Our implementation on Intel Tofino™ hardware demonstrates reliable time-based gating at line rate. Finally, we discuss how this periodicity mechanism can be extended to implement additional time-sensitive features such as the Time-Aware Shaper (TAS), offering a scalable foundation for deterministic network behavior in P4-based systems.

Speaker

Fabian Ihle received his bachelor’s (2021) and master’s degrees (2023) in computer science at the University of Tuebingen. Afterwards, he joined the communication networks research group of Prof. Dr. Habil Michael Menth as a Ph.D. student. His research interests include software-defined networking, P4-based data plane programming, resilience, and Time-Sensitive Networking (TSN).