Contributed by Bili Dong, Program Chair, 2026 P4 Workshop
This year marked the 10th annual P4 Workshop! It took place on October 12 at Google’s US-SVL-CRBN100 Building in Silicon Valley. It was my first time as program chair for the event and I am grateful to this year’s program committee members, especially Andy Fingerhut, for making this year’s program a great one!
Thank you to Michelle Roth, Emily Ruf, and Roxanne Joncas, for organizing the rest. Thank you as well to my colleagues at Google, to the catering team, the security team, and LF Events.
The recordings and slides are now available. Watch here
Keynotes
In the first keynote, Fast, Flexible, and Intelligent AI-Native Networks, Muhammad Shahbaz (University of Michigan) argued that P4 has solved the deterministic side of networking, connectivity, while security and performance are still left to fixed heuristics such as ECMP. He made the case for running machine learning directly in the data plane, so switches “enforce while learning” instead of waiting on a control plane that samples traffic and installs stale rules, and presented Taurus, a data-plane architecture that runs small models per packet at line rate, and Homunculus, a declarative framework that searches for a model that fits a given hardware target. He framed this as networking tracing the same fixed-function, programmable, domain-specific arc as computing, a few decades behind, and in need of its own domain-specific architecture for in-network inference. Slides PDF
Muhammad Shahbaz
Jiaxin Lin
In the second keynote, Data-Plane Programmability Across Heterogeneous Networks, Jiaxin Lin (Cornell University) looked at the same gap from the hardware side: without the right abstractions, every network engineer becomes a hardware engineer, once per target. She presented Alkali, a compiler framework that takes a single-threaded packet-processing program and automatically parallelizes it across very different SmartNICs, and then turned to scale-up GPU fabrics, where load/store traffic crosses switches that are almost entirely non-programmable today. Her proposal for bounded, verifiable “memory ops” that inspect, transform, multicast and reduce memory requests in the switch opens a new design space for the P4 community, and her answer to whether P4 should be the language there was “probably.” Slides PDF
Sessions
This year’s theme was “Building AI-Native Networks with P4,” and the twelve talks fell into three threads: what AI workloads need from the network, how new programmable silicon is opening up to P4, and how to make P4 systems trustworthy in production.
On the AI side, “Mind the Semantic Gap” by Deb Chatterjee (Qualcomm) proposed a minimal metadata contract through which AI applications tell the fabric what their flows mean; “In-Path Scalable Million-Flow Auditing” by Linfeng He ran per-flow accounting for a GPU fabric on two P4-programmed BlueField-3 DPUs instead of dozens of servers; “SmartRetry” by Pavani Kuppili (University of Utah) compared retry admission control in host XDP and on a P4 FPGA NIC; and “P4, XPUs and Device System Architecture” by Anjali Singhai Jain argued that PNA still cannot express a reliable transport and that P4 needs transactional semantics.
On the silicon side, “Adaptive Pipeline Configuration” by Laks Jayanthi (Cisco) showed one shared P4 application on Silicon One generating ACL microcode at runtime; “One PNA Pipeline, Multiple Control Domains” by Vivek Kashyap (Intel) called for standard precedence and isolation between the controllers that share an IPU pipeline; “Applets” by Venkat Pullela (AI Infrastructure) proposed levels at which a vendor can open a pipeline to partners; “XNA: Programming the X2 with P4” by Fabian Ruffy and Vladimir Gurevich (Xsight Labs) compiled conventional P4-16 onto a run-to-completion switch with an open instruction set; and “The Language and the Machine” by Ryan Goodfellow (Oxide) traced a production outage to a defective PHV container and made the case for published ISAs and register interfaces.
On verification and tooling, “P4 @ Google” by Ali Kheradmand and Jonathan Dilorenzo (Google) reviewed using P4 as both the controller’s schema and a specification from which switch tests are generated; “Aletheia” by Alborz Jelvani and Ali Kheradmand (Google) composed P4 switch models into a network-wide verifier; and “Beyond BMv2” by Matthew Lam and Victor Rios (Google) introduced 4ward, an open-source P4 simulator with PSA, v1model and PNA support. The day closed with updates from the four P4 working groups, including the conditional adoption of a formal, machine-checkable P4 specification.
If 2025 was the year P4 moved up the stack, 2026 was the year the two ends met in the middle: AI workloads asking the fabric to understand more, new and very different hardware adopting P4 as its programming model, and P4 increasingly used as a specification language rather than just a programming language.
2026 P4 Contributor Award
Steffen Smolka
Congratulations to Steffen Smolka (Google), the winner of this year’s Contributor Award.
“Thank you for this honor! P4 has been part of my life for a decade, from an internship at Barefoot Networks to building automated network validation tools at Google. Helping turn ideas from programming languages and formal methods into more reliable networks has been deeply rewarding. But what I’ll miss most is the people: thoughtful, generous collaborators who care about getting things right. As I step away from working on P4, I’m grateful for everything we built together and for the friendships along the way. P4 has already changed how we build and validate networks, and I believe its role—especially as a specification language—will only grow. I look forward to seeing what you build next.” — Steffen Smolka
Photos and Recording Playlist
