Date: February 4, 2026
Time: 8:00am Pacific
The exponential growth of cloud-native services, 5G connectivity, and data-intensive applications is driving unprecedented demand for high-throughput and flexible packet processing. Traditional fixed-function ASIC solutions, while performant, lack the adaptability to address emerging tunnelling protocols, dynamic QoS enforcement, and evolving custom workloads. P4, an open and protocol-independent programming language for the data plane, directly addresses these limitations by enabling developers to rapidly define and deploy advanced packet pipelines without RTL complexity. By combining FPGA Vendors P4 Compilers like Altera’s P4 Suite with iW-Fibre SmartNICs, operators can synthesize programmable pipelines that sustain line-rate performance while remaining fully adaptable.
Demonstration of the use cases – including checksum verification, IP-in-IP tunnelling, VXLAN encapsulation/decapsulation, and standards-based QoS metering—illustrate how P4 empowers service providers and data centers to stay agile, scalable, and future-ready.
Chethan T V is an Electronics an Communications Engineer possessing diverse experience in embedded industry as a digital design engineer with extensive expertise in FPGA design flow and SoC lifecycle. With strong project management skills, he has led various challenging projects from conceptualization stage to execution and delivered successful products in the field of defense, video, military & commercial sectors. He is an Associate Director, FPGA BU, iWave Global – leading the Smart-NIC division from the ground up, building a high-performing team, and driving strategic projects in next-generation networking.
