SIGCOMM 2026 | Programming SmartNICs Tutorial
August 17 @ 9:00 am - 1:00 pm
ACM SIGCOMM is the flagship annual conference of the ACM Special Interest Group on Data Communication (SIGCOMM). ACM SIGCOMM 2026, the 40th edition of the conference series, will be held between August 17 – 21, 2026, at the Colorado Convention Center in Denver, Colorado, USA.
Don’t miss this tutorial by P4 community members at the event on August 17.
Programming SmartNICs: From Packet Processing to Programmable Transport
Programmable switches transformed networking research by making the data plane accessible and programmable. A similar shift is now happening at the network edge: SmartNICs, DPUs, and IPUs are evolving into programmable computing platforms capable not only of packet processing, but also of stateful services and transport-layer functionality. Rather than being fixed-function offload devices, they are becoming heterogeneous subsystems tightly integrated with host software stacks.
This tutorial provides a unified, systems-oriented introduction to SmartNIC programmability, spanning four tightly coupled dimensions: data-plane packet processing, stateful network function design, transport-layer programmability, and host-level integration. It combines conceptual foundations with guided hands-on exercises on NVIDIA BlueField platforms using NVIDIA Launchpad, allowing participants to gain both architectural understanding and practical experience with packet-processing and transport programmability.
By the end of the tutorial, attendees will understand the design space across SmartNIC, DPU, and IPU platforms; write and deploy packet-processing logic on NIC targets; design and evaluate stateful services; experiment with transport-layer customization and programmable congestion control; and integrate NIC-based functionality with host control planes and software stacks.
Speakers:
- Fernando Ramos INESC-ID, IST, University of Lisbon
- Muhammad Shahbaz, University of Michigan
- Mina Tahmasbi Arashloo, University of Waterloo
- Mario Baldi, NVIDIA
Tutorial Schedule
9:00 – 9:45:SmartNIC Architectures and Programming Models
SmartNIC/DPU/IPU architectures; match-action pipelines vs. programmable cores vs. FPGA; Portable NIC Architecture (PNA); packet processing vs. transport programmability.
9:45 – 10:15: Packet Processing Programming on SmartNICs
Table lookups; packet transformations; control-plane integration. Programming with P4, DOCA Pipeline Language (DPL) and DOCA Flow.
10:15 – 10:45: Break
10:45 – 11:30 Transport Programming on SmartNICs
Hands-on development of packet-processing functionality, including forwarding, filtering, table lookups, and packet transformations, on BlueField-3 using DPL (DOCA Pipeline Language) and DOCA Flow to program the packet processing pipeline of the ConnectX-7 component.
11:30 – 12:00 Transport Programming on SmartNICs
Programmable congestion control; transport-layer extensions; host-NIC coordination; open research challenges.
12:00 – 12:45 Hands-On II: Transport Programmability on SmartNICs
Hands-on experimentation with programmable transport functionality using DOCA PCC (Programmable Congestion Control) and DPA (Data Path Accelerator) execution on BlueField-3; evaluating transport behavior and host-NIC interaction.
