Register to attend this P4 Developer Days webinar, “Gateway Use Case Architecture for Network Applications”
Date: August 6, 2025
Time: 8:00am Pacific
Abstract
Network applications demand ever-increasing performance and flexibility. Mapping P4 programs directly to FPGA hardware offers a powerful solution, but the design process can be complex. This presentation demonstrates a new toolchain for efficiently mapping P4 programs to Altera FPGAs, significantly accelerating gateway applications. Presentation leads attendees through the complete flow, from high-level P4 specification down to a fully synthesized FPGA design using a practical gateway example. Attendees will learn how this toolchain leverages p4 language capabilities to map the user application into FPGA. This session is ideal for network architects and hardware engineers seeking to leverage the power of P4 and FPGA acceleration for next-generation network applications.
Speaker
Pavel Benacek is Technical Lead at Altera with more than 12 years of experience in networking technology from research and industry. He is mainly working on hardware/software co-designs and high-level synthesis topics. He holds the Ph.D. at the Czech Technical University in Prague where he was working on theory of P4 language mapping to RTL design that can be synthesized to FPGA.