A presentation by the P4 Language Consortium and ONF in conjunction with CoNEXT 2020

Held online on December 1, 2020

EuroP4 2020 is the third P4 Language Consortium event in Europe. It aims to bring together P4 and P4->NetFPGA researchers from Europe and from around the world, and to foster the growth of the P4 Community.

Topics of an interest include, but are not limited to:

  • All aspects of P4-based network protocol research, including design, specification, verification, implementation, measurement, testing, and analysis.
  • Design, analysis, and evaluation of network architectures using P4 as a basis, e.g., specific algorithms and protocols for network virtualization or future Internet architectures.
  • New applications enabled by P4, including in-network computing and Big Data, Video and Virtual Reality, Mobile and Wireless Network Protocols and Applications, Ubiquitous computing, Internet-of-Things and Smart Cities.
  • Secure, reliable and dependable P4-based systems, including all aspects of monitoring, verification, debugging and troubleshooting networks enabled by P4.
  • P4-based and P4-NetFPGA based programmable data planes.
  • P4 end-host networking, offloading transport- and application-layer protocols to P4-enabled hardware.
  • Tools and frameworks for development using P4.
  • Contributions to the evolution of the P4 language.

Important Dates

Abstract registration: Tuesday September 1st, 2020 (11:59PM AoE)
Abstract registration and Paper submission deadline: Tuesday, September 8th, 2020 (11:59PM AoE)
Acceptance notification: Monday, October 5th, 2020
Posters and demos deadline: Tuesday, September 8th, 2020 (11:59PM AoE)
Posters and demos notification: Monday, October 5th, 2020.
Camera ready: Thursday, October 29th, 2020 (11:59PM AoE)


As a consequence of the current situation of the COVID-19 pandemic and similar to CoNEXT’20, EuroP4’20 will be a fully virtual (online) event. Please follow the updates on the CoNEXT’20 and our website for the details.

Accepted papers

  • Comparative Evaluation of IP-Address Anti-Spoofing Mechanisms using a P4/NetFPGA-based Switch. Harsh Gondaliya (SRM Institute of Science and Technology), Ganesh C. Sankaran (University of California, Davis), Krishna Sivalingam (Indian Institute of Technology Madras)

  • Falcon - Low Latency, Network-Accelerated Scheduling. Ibrahim Kettaneh (University of Waterloo), Sreeharsha Udayashankar (University of Waterloo), Ashraf Abdel-hadi (University of Waterloo), Samer Al-Kiswany (University of Waterloo)

  • SYN Flood Defense in Programmable Data Planes. Dominik Scholz (Technical University of Munich), Sebastian Gallenmüller (Technical University of Munich), Henning Stubbe (Technical University of Munich), Georg Carle (Technical University of Munich)

  • Leveraging Target-specific Features Through P4. Alex Seibulescu (Pensando Systems, Inc.), Mario Baldi (Pensando Systems, Inc.)

  • P4-Protect: 1+1 Path Protection for P4. Steffen Lindner (University of Tuebingen), Daniel Merling (University of Tuebingen), Marco Häberle (University of Tuebingen), Michael Menth (University of Tuebingen)

  • MTPSA: Multi-Tenant Programmable Switches. Radostin Stoyanov (University of Cambridge), Noa Zilberman (University of Oxford)

  • Compiling Packet Programs to Reconfigurable Switches: Theory and Algorithms. Balázs Vass (Budapest University of Technology and Economics), Erika Bérczi-Kovács (Eötvös Loránd Science University), Costin Raiciu (University Politehnica of Bucharest), Gábor Rétvári (Budapest University of Technology and Economics)

Accepted demos

  • A P4 Data Plane for the Quantum Internet Wojciech Kozlowski (QuTech, Delft University of Technology), Fernando Kuipers (Delft University of Technology), Stephanie Wehner (QuTech, Delft University of Technology)

  • Developing EFSM-based stateful applications with FlowBlaze.p4 and ONOS. Daniele Moro (Politecnico di Milano), Davide Sanvito (NEC Laboratories Europe), Antonio Capone (Politecnico di Milano)

  • Pushing Network Programmability to the Limits with SRv6 uSID and P4. Ahmed Abdelsalam (Cisco Systems), Angelo Tulumello (University of Rome Tor Vergata), Marco Bonola (CNIT – National Inter University Consortium for Telecommunications), Stefano Salsano (University of Rome Tor Vergata), Clarence Filsfils (Cisco Systems)

Accepted posters

  • Unleashing the performance of virtual BNG by offloading data plane to a programmable ASIC. Tomasz Osiński (Orange Labs & Warsaw University of Technology), Mateusz Kossakowski (Orange Labs), Mateusz Pawlik (Orange Labs), Jan Palimąka (Orange Labs), Michał Sala (Orange Labs), Halina Tarasiuk (Warsaw University of Technology)

  • Towards a Hybrid Next Generation NodeB. Péter Vörös (Eötvös Loránd University), Gergely Pongrácz (Ericsson Research), Sándor Laki (Eötvös Loránd University)

  • A perspective on P4-based data and control plane modularity for network automation. Eder Ollora Zaballa (Technical University of Denmark), David Franco (University of the Basque Country), Michael Stübert Berger (Denmark Techinical University), Mariavi Higuero (University of the Basque Country)


Registration is through CoNEXT 2020

General Chairs

Noa Zilberman, University of Cambridge
Robert Soulé, Yale University

Program Chairs

Fernando Ramos, University of Lisbon
Gabor Retvari, Budapest University of Technology and Economics

Technical Program Committee

Aurojit Panda, New York University
Ben Pfaff, VMware
Brian O’Connor, Open Networking Foundation
Christian Rothenberg, University of Campinas
Gianni Antichi, Queen Mary University of London
Gordon Brebner, Xilinx Labs
Jon Crowcroft, University of Cambridge
Marco Chiesa, KTH Royal Institute of Technology
Mario Baldi, Pensando Systems & Politecnico di Torino
Mina Tahmasbi Arashloo, Cornell University
Nate Foster, Cornell University
Paolo Costa, Microsoft Research
Roberto Bifulco, NEC Labs Europe
Sandor Laki, Eötvös Loránd University
Shir Landau Feibish, Princeton University
Theo Jepsen, Stanford University