A presentation by the P4 Language Consortium and ONF in conjunction with ICNP 2018

Held at Cambridge, UK on September 24, 2018

P4WE 2018 is the first P4 Language Consortium event in European. It aims to bring together P4 and P4->NetFPGA researchers from Europe and from around the world, and to foster the growth of the P4 Community.

P4WE, which will run as a workshop at ICNP 2018, will have proceedings. It aims to enable researchers to publish early stage work and small scale projects.


University of Cambridge
Department of Computer Science and Technology
The Computer Laboratory
William Gates Building
15 JJ Thomson Avenue, Cambridge CB3 0FD

Maps and directions


Registration is through ICNP 2018


  • 8:30 - 9:00am

    • Registration and Breakfast

  • 9:00 - 9:15

    • Welcome and Introductions

  • 9:15 - 10:15

    • Keynote: Extending the range of P4 programmability (slides)

      Speaker: Professor Gordon Brebner (Xilinx Labs)

      Abstract In four years, P4 has evolved from being a paper proposal to being a packet processing programming language with increasing adoption worldwide, overseen by the P4 Language Consortium (P4.org). The talk will first overview developments over this period, which have brought the community to the current P4_16 language specification, the PSA (Portable Switch Architecture) specification, and the P4Runtime API specification. It will then discuss some current community efforts to extend the reach of P4. One of the key developments in 2017 was language-architecture separation, leading to the P4_16 (language) and PSA (architecture) threads. In practice, NICs (Network Interface Cards, notably Smart NICs) are a common target, so one community goal is to define a PNA (portable NIC architecture) specification, to complement the existing PSA specification. Then, a bigger picture is to extend P4 to allow the description of architectures, which is the goal of the Programmable Target Architecture (PTA) research project of Stanford and Xilinx Labs. The talk will describe this project, and a current prototype that compiles extended P4 descriptions to FPGA-based hardware implementations. An important test case for the new approach will be the expression of both PSA and PNA (when ultimately defined) in the extended “P4 +” rather than in English as currently. Currently, P4 is focused on packet processing – through parsing, match-action pipelines, and deparsing. Another current research project, involving MIT, NYU, Stanford, and Xilinx Labs, concerns extending P4 (language and architecture) to cover Traffic Management – providing programmable scheduling, shaping, policing, queueing, etc. The talk will overview this project, and a current prototype based on the PIFO scheduling model that was presented at SIGCOMM 2016. Finally, the talk will consider future evolution of the open source community around P4, including the development of comprehensive reference examples for both switch and NIC architectures, for both software and programmable hardware implementations.
      Biography Gordon Brebner is a Distinguished Engineer at Xilinx, Inc., the technology leader in highly flexible and adaptive processing platforms. He works in Xilinx Labs, leading an international group researching issues surrounding networked and trusted processing systems of the future. His main personal research interests concern dynamically reconfigurable architectures, domain-specific languages with highly concurrent implementations, and high performance networking and telecommunications. His group’s research led to the Xilinx SDNet product for P4-programmable networking at scalable 1G to 1T rates. He holds around 40 patents, and has published around 60 papers, in the general area of networking with FPGAs. Prior to joining Xilinx in 2002, he was the Professor of Computer Systems and Head of the Department of Computer Science at the University of Edinburgh, and remains an Honorary Professor of Informatics there. He is an active contributor to the P4 language Consortium (P4.org), including co-chairing the P4 Language Design working group from its inception. He received the inaugural P4.org Distinguished Service Award in 2018.

  • 10:15 - 10:45

    • Coffee break

  • 10:45 - 12:15

    • Named Data Networks using Programmable Switches. Rui Muigel (University of Lisbon), Salvatore Signorello (University of Luxembourg), Fernando M. V. Ramos (University of Lisbon) (slides)

    • Consensus for Non-Volatile Main Memory. Huynh Tu Dang (Università della Svizzera italiana), Jaco Hofmann (TU Darmstadt), Yang Liu (Western Digital Research), Marjan Radi (Western Digital Research), Dejan Vucinic (Western Digital Research), Fernando Pedone (Università della Svizzera italiana), Robert Soulé (Università della Svizzera italiana) (slides)

    • Transparent Edge Gateway for Mobile Networks. Ashkan Aghdai (NYU), Mark Huang (Huawei), David H. Dai (Huawei), Yang Xu (NYU), H. Jonathan Chao (NYU) (slides)

  • 12:15 - 13:30

    • Lunch break

  • 13:30 - 14:40

    • Panel: P4 Education

  • 14:40 - 15:20

    • Lightning talks

  • 15:20 - 16:15

    • Coffee break and Posters

  • 16:15 - 17:30

    • Stateless Load-Aware Load Balancing in P4. Benoit Pit–Claudel (Cisco Systems, École Polytechnique), Yoann Desmouceaux Cisco Systems, École Polytechnique), Pierre Pfister (Cisco Systems), Marc Townsley (Cisco Systems) (slides)

    • P4LLVM: An LLVM based P4 Compiler. Dangeti Tharun Kumar, S Venkata Keerthy, Ramakrishna Upadrasta (IIT Hyderabad) (slides)

    • pcube: Primitives for network data plane programming. Rinku Shah, Aniket Shirke, Akash Trehan, Mythili Vutukuru, Purushottam Kulkarni (IIT Bombay) (slides)

  • 17:30 - 17:45

    • Closing

Accepted Posters

  • Network Coding for Critical Infrastructure Networks. Rakesh Kumar, Vignesh Babu, David M. Nicol (University of Illinois, Urbana-Champaign) (slides)

  • ARP-P4: A hybrid ARP-Path/P4Runtime switch. Isaias Martinez-Yelmo, Joaquin Alvarez-Horcajo, Miguel Briso-Montiano, Diego Lopez-Pajares, Elisa Rojas (University of Alcalá) (slides)

  • One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. Jeferson Santiago da Silva, Thibaut Stimpfling, Thomas Luinaud, Bachir Fradj (Polytechnique Montréal), Bochra Boughzala (Kaloom Inc.) (slides)

  • Using P4 and Source Based Routing To Enable Performant Intents in Software Defined Networks. Benjamin Lewis, Lyndon Fawcett, Dr. Matthew Broadbent, Prof. Nicholas Race (Lancaster University)

  • Verification of Generated RTL from P4 Source Code. Radek Iša, Pavel Benáček (CESNET a.l.e.), Viktor Puš (Netcope Technologies) (slides)

  • A P4-Based PON Architecture for 5G. Adebanjo Haastrup, David Rincon, Sallent Sebastia, J. Ramon Piney (Universitat Politècnica de Catalunya) (slides)

  • Implementation of Sketch-based Entropy Estimation for Network Traffic Analysis Using P4. Ku-Yeh Shih, Yu-Kuen Lai, Theophilus Wellem, Ho-Ping Lee, Po-Yu Huang, Yu-Jau Lin (Chung Yuan Christian University) (slides)

  • The P4->NetFPGA Workflow, and Experience Report from the Stanford CS344 Class. Stephen Ibanez, Nick McKeown (Stanford University), Gordon Brebner (Xilinx Labs) (slides)

Accepted Demos

  • Hardware-Accelerated Firewall for 5G Mobile Networks. Ruben Ricart-Sanchez (University of the West of Scotland), Pedro Malagon (Universidad Politecnica de Madrid), Jose M. Alcaraz-Calero (University of the West of Scotland), Qi Wang (University of the West of Scotland) (slides)

  • Switch ASIC Programmability in Hybrid Mode. Matty Kadosh, Alan Lo, Yonatan Piasetzky, Omer Shabtai, Marian Pritsak (Mellanox Technologies), Guohan Lu (Microsoft) (slides)

  • RAYMAX P4-Enabled SmartNIC: Providing Service-Driven Data Center Networking. Yan Yan, Shen Tan (Raymax Technology), Reza Nejabati, Dimitra Simeonidou (University of Bristol) (slides)

  • VNF offloading on a multi-vendor P4 fabric controlled by ONOS via P4Runtime. Andrea Campanella, Carmelo Cascone (Open Networking Foundation) (slides)

  • Network-assisted sorting. Petar Penkov, Hristo Stoyanov (Stanford University)


Registration is through ICNP 2018

Travel Grants

Refer to ICNP travel grants page

Technical Program Committee

  • Noa Zilberman (chair), University of Cambridge
  • Robert Soulé (chair), Università della Svizzera italiana
  • Gianni Antichi, University of Cambridge
  • Mario Baldi, Cisco
  • Gordon Brebner, Xilinx Labs
  • Paolo Costa, Microsoft Research
  • Andy Fingerhut, Cisco Systems
  • Nate Foster, Cornell University
  • Timothy Griffin, University of Cambridge
  • Mukesh Hira, VMWare
  • Masoud Moshref, Barefoot Networks
  • Fernando Ramos, University of Lisbon
  • Christian Esteve Rothenberg, University of Campinas

Special Thanks to our Sponsors:

Gold Level:

Western Digital Xilinx

Silver Level:

Barefoot Networks

Bronze Level:

Microsoft Stordis

Contact the workshop chairs for sponsorship opportunities.