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X-WR-CALNAME:P4 - Language Consortium
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X-WR-CALDESC:Events for P4 - Language Consortium
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TZOFFSETFROM:+0000
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DTSTART:20170101T000000
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DTSTART;TZID=UTC:20180924T083000
DTEND;TZID=UTC:20180924T174500
DTSTAMP:20260426T114709
CREATED:20250912T220013Z
LAST-MODIFIED:20250915T231422Z
UID:10000096-1537777800-1537811100@p4.org
SUMMARY:1st P4 Workshop in Europe (P4WE)
DESCRIPTION:A presentation by the P4 Language Consortium and ONF in conjunction with ICNP 2018\nHeld at Cambridge\, UK on September 24\, 2018\nP4WE 2018 is the first P4 Language Consortium event in European. It aims to bring together P4 and P4->NetFPGA researchers from Europe and from around the world\, and to foster the growth of the P4 Community. \nP4WE\, which will run as a workshop at ICNP 2018\, will have proceedings. It aims to enable researchers to publish early stage work and small scale projects. \nVenue\nUniversity of Cambridge\nDepartment of Computer Science and Technology\nThe Computer Laboratory\nWilliam Gates Building\n15 JJ Thomson Avenue\, Cambridge CB3 0FD \nAgenda\n\n\n8:30 – 9:00am\n\nRegistration and Breakfast\n\n\n\n\n\n9:00 – 9:15\n\nWelcome and Introductions\n\n\n\n\n\n9:15 – 10:15\n\nKeynote: Extending the range of P4 programmability (slides)Speaker: Professor Gordon Brebner (Xilinx Labs)\n\n\n\n\n\n10:15 – 10:45\n\nCoffee break\n\n\n\n\n\n10:45 – 12:15\n\nNamed Data Networks using Programmable Switches. Rui Muigel (University of Lisbon)\, Salvatore Signorello (University of Luxembourg)\, Fernando M. V. Ramos (University of Lisbon) (slides)\nConsensus for Non-Volatile Main Memory. Huynh Tu Dang (Università della Svizzera italiana)\, Jaco Hofmann (TU Darmstadt)\, Yang Liu (Western Digital Research)\, Marjan Radi (Western Digital Research)\, Dejan Vucinic (Western Digital Research)\, Fernando Pedone (Università della Svizzera italiana)\, Robert Soulé (Università della Svizzera italiana) (slides)\nTransparent Edge Gateway for Mobile Networks. Ashkan Aghdai (NYU)\, Mark Huang (Huawei)\, David H. Dai (Huawei)\, Yang Xu (NYU)\, H. Jonathan Chao (NYU) (slides)\n\n\n\n\n\n12:15 – 13:30\n\nLunch break\n\n\n\n\n\n13:30 – 14:40\n\nPanel: P4 Education\n\n\n\n\n\n14:40 – 15:20\n\nLightning talks\n\n\n\n\n\n15:20 – 16:15\n\nCoffee break and Posters\n\n\n\n\n\n16:15 – 17:30\n\nStateless Load-Aware Load Balancing in P4. Benoit Pit–Claudel (Cisco Systems\, École Polytechnique)\, Yoann Desmouceaux Cisco Systems\, École Polytechnique)\, Pierre Pfister (Cisco Systems)\, Marc Townsley (Cisco Systems) (slides)\nP4LLVM: An LLVM based P4 Compiler. Dangeti Tharun Kumar\, S Venkata Keerthy\, Ramakrishna Upadrasta (IIT Hyderabad) (slides)\npcube: Primitives for network data plane programming. Rinku Shah\, Aniket Shirke\, Akash Trehan\, Mythili Vutukuru\, Purushottam Kulkarni (IIT Bombay) (slides)\n\n\n\n\n\n17:30 – 17:45\n\nClosing\n\n\n\n\nAccepted Posters\n\nNetwork Coding for Critical Infrastructure Networks. Rakesh Kumar\, Vignesh Babu\, David M. Nicol (University of Illinois\, Urbana-Champaign) (slides)\nARP-P4: A hybrid ARP-Path/P4Runtime switch. Isaias Martinez-Yelmo\, Joaquin Alvarez-Horcajo\, Miguel Briso-Montiano\, Diego Lopez-Pajares\, Elisa Rojas (University of Alcalá) (slides)\nOne for All\, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. Jeferson Santiago da Silva\, Thibaut Stimpfling\, Thomas Luinaud\, Bachir Fradj (Polytechnique Montréal)\, Bochra Boughzala (Kaloom Inc.) (slides)\nUsing P4 and Source Based Routing To Enable Performant Intents in Software Defined Networks. Benjamin Lewis\, Lyndon Fawcett\, Dr. Matthew Broadbent\, Prof. Nicholas Race (Lancaster University)\nVerification of Generated RTL from P4 Source Code. Radek Iša\, Pavel Benáček (CESNET a.l.e.)\, Viktor Puš (Netcope Technologies) (slides)\nA P4-Based PON Architecture for 5G. Adebanjo Haastrup\, David Rincon\, Sallent Sebastia\, J. Ramon Piney (Universitat Politècnica de Catalunya) (slides)\nImplementation of Sketch-based Entropy Estimation for Network Traffic Analysis Using P4. Ku-Yeh Shih\, Yu-Kuen Lai\, Theophilus Wellem\, Ho-Ping Lee\, Po-Yu Huang\, Yu-Jau Lin (Chung Yuan Christian University) (slides)\nThe P4->NetFPGA Workflow\, and Experience Report from the Stanford CS344 Class. Stephen Ibanez\, Nick McKeown (Stanford University)\, Gordon Brebner (Xilinx Labs) (slides)\n\nAccepted Demos\n\nHardware-Accelerated Firewall for 5G Mobile Networks. Ruben Ricart-Sanchez (University of the West of Scotland)\, Pedro Malagon (Universidad Politecnica de Madrid)\, Jose M. Alcaraz-Calero (University of the West of Scotland)\, Qi Wang (University of the West of Scotland) (slides)\nSwitch ASIC Programmability in Hybrid Mode. Matty Kadosh\, Alan Lo\, Yonatan Piasetzky\, Omer Shabtai\, Marian Pritsak (Mellanox Technologies)\, Guohan Lu (Microsoft) (slides)\nRAYMAX P4-Enabled SmartNIC: Providing Service-Driven Data Center Networking. Yan Yan\, Shen Tan (Raymax Technology)\, Reza Nejabati\, Dimitra Simeonidou (University of Bristol) (slides)\nVNF offloading on a multi-vendor P4 fabric controlled by ONOS via P4Runtime. Andrea Campanella\, Carmelo Cascone (Open Networking Foundation) (slides)\nNetwork-assisted sorting. Petar Penkov\, Hristo Stoyanov (Stanford University)\n\nTechnical Program Committee\n\nNoa Zilberman (chair)\, University of Cambridge\nRobert Soulé (chair)\, Università della Svizzera italiana\nGianni Antichi\, University of Cambridge\nMario Baldi\, Cisco\nGordon Brebner\, Xilinx Labs\nPaolo Costa\, Microsoft Research\nAndy Fingerhut\, Cisco Systems\nNate Foster\, Cornell University\nTimothy Griffin\, University of Cambridge\nMukesh Hira\, VMWare\nMasoud Moshref\, Barefoot Networks\nFernando Ramos\, University of Lisbon\nChristian Esteve Rothenberg\, University of Campinas\n\nSpecial Thanks to our Sponsors:\n\n\n\n\nGold Level:\n\n\n\n\n\n\nSilver Level:\n\n\n\n\n\nBronze Level:\n\n\n\n\n\n\n 
URL:https://p4.org/event/1st-p4-workshop-in-europe-p4we/
CATEGORIES:Events
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