P4 Developer Days - QuIP: A P4 Quantum Internet Protocol Prototyping Framework
2025-12-03 08:00 UTC
P4 Developer Days webinar, “QuIP: A P4 Quantum Internet Protocol Prototyping Framework”
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Abstract

Quantum entanglement is so fundamentally different from a network packet that several quantum network stacks have been proposed; one of which has even been experimentally demonstrated. Several simulators have also been developed to make up for limited hardware availability, and which facilitate the design and evaluation of quantum network protocols. However, the lack of shared tooling and community-agreed node architectures has resulted in protocol implementations that are tightly coupled to their simulators. Besides limiting their reusability between different simulators, it also makes building upon prior results and simulations difficult. To address this problem, we have developed QuIP: a P4-based Quantum Internet Protocol prototyping framework for quantum network protocol design. QuIP is a framework for designing and implementing quantum network protocols in a platform-agnostic fashion. It achieves this by providing the means to flexibly, but rigorously, define device architectures against which quantum network protocols can be implemented in the network programming language P416. QuIP also comes with the necessary tooling to enable their execution in existing quantum network simulators. We demonstrate its use by showcasing V1Quantum, a completely new device architecture, implementing a link- and network-layer protocol, and simulating it in the existing simulator NetSquid.
Speaker
Wojciech Kozlowski is the Quantum Communication Topic Lead at SURF. He completed his MSci in Theoretical Quantum Physics at the University of Cambridge and his PhD in Atomic and Laser Physics at the University of Oxford. Since then, Wojciech has been involved with networks, both classical and quantum. After his PhD he joined Metaswitch in London where he worked as a software engineer developing (classical) control planes. In 2019, Wojciech moved to the Netherlands where he worked as a postdoc and later quantum network engineer at the TU Delft before joining SURF in 2024.

P4 Developer Days - Programmable Hardware Emulation Environment for Realistic and Scalable Network Testing
2025-12-10 08:00 UTC
P4 Developer Days: “Programmable Hardware Emulation Environment for Realistic and Scalable Network Testing”
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Abstract
Network emulators are essential for testing and validating new networking solutions before deployment. In this presentation, we will showcase a hardware-based emulation framework that brings programmable switches and SmartNIC awareness to network experimentation. Our environment enables realistic and scalable evaluation of offloading, host interaction, and in-network processing. Through a simple API, researchers can define and deploy multi-switch, multi-host topologies; configure diverse link characteristics (e.g., bandwidth, latency, packet loss); and generate realistic traffic patterns. Finally, we validate the environment using multiple state-of-the-art scenarios, assessing robustness by reproducing and extending prior experiments across an expanded evaluation space.
Speakers
Fabricio Rodriguez received the M.Sc. and Ph.D. degrees in Electrical Engineering from the Universidade Estadual de Campinas in 2018 and 2024, respectively. He was a researcher with the Information Networking Technologies Research Innovation Group (INTRIG), participating in projects with Ericsson, Padtec, and RNP. He is currently a Research Scientist at Telefónica Research, Spain. His research interests include programmable networks, in-network applications, security, and network performance.

Francisco Vogt received the bachelor’s degree in computer science from the Federal University of Pampa and the master’s degree in computer engineering from the Universidade Estadual de Campinas, Brazil, where he is currently pursuing the Ph.D. degree in electrical engineering. He is currently a Visiting Researcher with the University of Amsterdam and works with the Multiscale Networked Systems (MNS) Research Group. He is involved as a Researcher with Ericsson on the project “SMARTNESS 2030: SMART NEtworks and ServiceS for 2030.” His research interests include programmable networks, network monitoring, network function offloading, and network testing.
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P4 Developer Days - In-Network Inference with P4: From Stateless to Hybrid Approaches
2026-01-21 08:00 UTC
P4 Developer Days webinar, “In-Network Inference with P4: From Stateless to Hybrid Approaches”
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Abstract
In-network machine learning (ML) techniques employ the P4 language to embed trained ML models directly into programmable network data planes. This has enabled novel applications in network security, routing optimization, and traffic classification, amongst others. This presentation charts the evolution of these techniques, starting with stateless, packet-level inference models like Henna. It then explores the shift to stateful, flow-level approaches as demonstrated in Flowrest. The talk culminates with Jewel, a novel hybrid system that performs joint packet and flow-level inference for improved accuracy and efficiency. This journey from stateless to hybrid methodologies highlights the advancements and trade-offs in building intelligent, high-performance, and ML-empowered networks with P4.

Speaker
Aristide Akem is a Lecturer in Computer Science within the Cyberphysical Systems Group in the School of Electronics and Computer Science at the University of Southampton. Before joining Southampton, he was a postdoctoral researcher in the Computing Infrastructure Group at the University of Oxford. His research spans machine learning, network programming with P4, and mobile networking, with applications in network security, IoT, and energy. He earned his PhD from Universidad Carlos III de Madrid and IMDEA Networks Institute, following a Master of Science in Electrical and Computer Engineering from Carnegie Mellon University Africa, and a Master’s in Telecommunications Engineering from the University of Yaounde I.

P4 Developer Days - Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA based SmartNICs
2026-02-04 08:00 - 09:00 UTC
In case you missed it, you can now view the recording of this P4 Developer Days webinar, “Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA-based SmartNICs”

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Abstract
The exponential growth of cloud-native services, 5G connectivity, and data-intensive applications is driving unprecedented demand for high-throughput and flexible packet processing. Traditional fixed-function ASIC solutions, while performant, lack the adaptability to address emerging tunnelling protocols, dynamic QoS enforcement, and evolving custom workloads. P4, an open and protocol-independent programming language for the data plane, directly addresses these limitations by enabling developers to rapidly define and deploy advanced packet pipelines without RTL complexity. By combining FPGA Vendors P4 Compilers like Altera’s P4 Suite with iW-Fibre SmartNICs, operators can synthesize programmable pipelines that sustain line-rate performance while remaining fully adaptable.
Demonstration of the use cases – including checksum verification, IP-in-IP tunnelling, VXLAN encapsulation/decapsulation, and standards-based QoS metering—illustrate how P4 empowers service providers and data centers to stay agile, scalable, and future-ready.
Speaker
Chethan T V is an Electronics an Communications Engineer possessing diverse experience in embedded industry as a digital design engineer with extensive expertise in FPGA design flow and SoC lifecycle. With strong project management skills, he has led various challenging projects from conceptualization stage to execution and delivered successful products in the field of defense, video, military & commercial sectors. He is an Associate Director, FPGA BU, iWave Global – leading the Smart-NIC division from the ground up, building a high-performing team, and driving strategic projects in next-generation networking.

P4 Developer Days - P4Muse (P4 Modularity and Unification for Seamless Extensibility)
2026-03-04 08:00 - 09:00 (America/Vancouver)
Register to attend this P4 Developer Days webinar, “P4Muse (P4 Modularity and Unification for Seamless Extensibility”
Date: March 4, 2026
Time: 8:00am Pacific
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Abstract

Domain-specific programming languages such as P4 enable flexible and high-performance packet processing in programmable network data planes. However, most P4 programs remain monolithic, limiting the development of modular and reusable protocols and libraries. Introducing modularity to P4 has been challenging because existing approaches—such as trans-compilers and virtualization—operate outside the P4 language and compiler, reducing backward compatibility and extensibility. P4Muse (P4 Modularity and Unification for Seamless Extensibility) addresses this challenge by introducing a compiler-managed approach to modularity within the P4C compiler. Without requiring any new syntax or annotations, P4Muse introduces new compiler passes for automatic code merging, enabling modular design, reuse, and seamless integration of complex network functionalities. Our results show that P4Muse effectively supports modular P4 program development without altering existing P4 syntax, providing a robust solution that significantly improves code reusability, flexibility, and extensibility while maintaining backward compatibility.

Speakers
Mohsen Rahmati is a Ph.D. candidate in Computer Engineering at Polytechnique Montréal, supervised by Professors Yvon Savaria, François-Raymond Boyer, and Jean-Pierre David. His research focuses on compiler design for programmable networks, emphasizing modularity and reusability in the P4 language. He is the creator of P4Muse, a compiler-managed modularity framework (accepted in IEEE Access, 2025), and P4O2, an object-oriented-inspired modularity in P4 currently under review at IEEE Access.

François-Raymond Boyer received B.Sc. and Ph.D. degrees in computer science from Université de Montréal, Montreal, QC, Canada, in 1996 and 2001, respectively. Since 2001, he has been with Polytechnique Montréal, Montréal, where he is currently a Professor with the Department of Computer and Software Engineering. He has authored or co-authored more than 30 conference and journal papers. His current research interests include microelectronics, performance optimization, parallelizing compilers, digital audio, and body motion capture. He is a member of Regroupement Stratégique en Microélectronique du Québec, Groupe de Recherche en Microélectronique et Microsystèmes, and Observatoire Interdisciplinaire de Création et de Recherche en Musique.

P4 Developer Days - SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate
2026-03-19 08:00 - 09:00 UTC
Register to attend this P4 Developer Days webinar, “SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate”

March 19 at 11 am ET/4 pm CET

Abstract
Machine learning is increasingly used in programmable data planes, such as switches and smartNICs, to enable real-time traffic analysis and security monitoring at line rate. Decision trees (DTs) are particularly well-suited for these tasks due to their interpretability and compatibility with the Reconfigurable Match-Action Table (RMT) architecture. However, current DT implementations require collecting all features upfront, which limits scalability and accuracy due to constrained data plane resources. This paper introduces SpliDT, a scalable framework that reimagines DT deployment as a partitioned inference problem over a sliding window of packets.
By dividing inference into sequential subtrees—each using its own set of top-k features—SpliDT supports more stateful features without exceeding hardware limits. An in-band control channel manages transitions between subtrees and reuses match keys and registers across partitions, implemented using P4 for packet recirculation and control-plane coordination. This design allows physical resources to be shared efficiently while maintaining line-rate processing. To maximize accuracy and scalability, SpliDT employs a custom training and design-space-exploration (DSE) workflow that jointly optimizes feature allocation, tree depth, and partitioning. Evaluations show that SpliDT supports up to 5x more features, scales to millions of flows, and outperforms baselines, with low overhead and minimal time-to-detection (TTD).

Speaker
Murayyiam Parvez is a Ph.D. candidate in the Department of Computer Science at Purdue University, advised by Professor Muhammad Shahbaz and Professor Sonia Fahmy. Her research focuses on designing the next generation of hybrid software–hardware abstractions and architectures for emerging network security and machine learning applications, with an emphasis on leveraging programmable switches to enable high-performance, in-network intelligence.

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