P4 Developer Days - P4Muse (P4 Modularity and Unification for Seamless Extensibility)
2026-03-04 08:00 - 09:00 (America/Vancouver)
Register to attend this P4 Developer Days webinar, “P4Muse (P4 Modularity and Unification for Seamless Extensibility”
Date: March 4, 2026
Time: 8:00am Pacific
Slides (PDF) | Watch Recording
Abstract

Domain-specific programming languages such as P4 enable flexible and high-performance packet processing in programmable network data planes. However, most P4 programs remain monolithic, limiting the development of modular and reusable protocols and libraries. Introducing modularity to P4 has been challenging because existing approaches—such as trans-compilers and virtualization—operate outside the P4 language and compiler, reducing backward compatibility and extensibility. P4Muse (P4 Modularity and Unification for Seamless Extensibility) addresses this challenge by introducing a compiler-managed approach to modularity within the P4C compiler. Without requiring any new syntax or annotations, P4Muse introduces new compiler passes for automatic code merging, enabling modular design, reuse, and seamless integration of complex network functionalities. Our results show that P4Muse effectively supports modular P4 program development without altering existing P4 syntax, providing a robust solution that significantly improves code reusability, flexibility, and extensibility while maintaining backward compatibility.

Speakers
Mohsen Rahmati is a Ph.D. candidate in Computer Engineering at Polytechnique Montréal, supervised by Professors Yvon Savaria, François-Raymond Boyer, and Jean-Pierre David. His research focuses on compiler design for programmable networks, emphasizing modularity and reusability in the P4 language. He is the creator of P4Muse, a compiler-managed modularity framework (accepted in IEEE Access, 2025), and P4O2, an object-oriented-inspired modularity in P4 currently under review at IEEE Access.

François-Raymond Boyer received B.Sc. and Ph.D. degrees in computer science from Université de Montréal, Montreal, QC, Canada, in 1996 and 2001, respectively. Since 2001, he has been with Polytechnique Montréal, Montréal, where he is currently a Professor with the Department of Computer and Software Engineering. He has authored or co-authored more than 30 conference and journal papers. His current research interests include microelectronics, performance optimization, parallelizing compilers, digital audio, and body motion capture. He is a member of Regroupement Stratégique en Microélectronique du Québec, Groupe de Recherche en Microélectronique et Microsystèmes, and Observatoire Interdisciplinaire de Création et de Recherche en Musique.

P4 Developer Days - SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate
2026-03-19 08:00 - 09:00 UTC
Register to attend this P4 Developer Days webinar, “SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate”
March 19 at 11 am ET/4 pm CET
Slides (PDF) || Watch Recording

Abstract
Machine learning is increasingly used in programmable data planes, such as switches and smartNICs, to enable real-time traffic analysis and security monitoring at line rate. Decision trees (DTs) are particularly well-suited for these tasks due to their interpretability and compatibility with the Reconfigurable Match-Action Table (RMT) architecture. However, current DT implementations require collecting all features upfront, which limits scalability and accuracy due to constrained data plane resources. This paper introduces SpliDT, a scalable framework that reimagines DT deployment as a partitioned inference problem over a sliding window of packets.
By dividing inference into sequential subtrees—each using its own set of top-k features—SpliDT supports more stateful features without exceeding hardware limits. An in-band control channel manages transitions between subtrees and reuses match keys and registers across partitions, implemented using P4 for packet recirculation and control-plane coordination. This design allows physical resources to be shared efficiently while maintaining line-rate processing. To maximize accuracy and scalability, SpliDT employs a custom training and design-space-exploration (DSE) workflow that jointly optimizes feature allocation, tree depth, and partitioning. Evaluations show that SpliDT supports up to 5x more features, scales to millions of flows, and outperforms baselines, with low overhead and minimal time-to-detection (TTD).

Speaker
Murayyiam Parvez is a Ph.D. candidate in the Department of Computer Science at Purdue University, advised by Professor Muhammad Shahbaz and Professor Sonia Fahmy. Her research focuses on designing the next generation of hybrid software–hardware abstractions and architectures for emerging network security and machine learning applications, with an emphasis on leveraging programmable switches to enable high-performance, in-network intelligence.

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P4 Developer Days – EdgeP4: In-Network Edge Intelligence for a Tactile Cyber-Physical System Testbed Across Cities
2026-05-20 08:00 - 09:00 (America/Vancouver)
Register to attend this P4 Developer Day webinar on May 27 at 11 am ET/5 pm CET
EdgeP4: In-Network Edge Intelligence for a Tactile Cyber-Physical System Testbed Across Cities

Abstract
Tactile Internet based operations, e.g., telesurgery, rely on the human operator for end-to-end closed loop control to achieve accuracy. While feedback and control are subject to network latency and packet loss, critical operations such as pose correction, fiducial marking, tremor reduction, etc. are tasks that should be carried out automatically and thus dispensing with these feedback signals from traversing the network to the other end. We design two edge intelligence algorithms hosted at P4 programmable end switches placed 400 km apart. These algorithms locally compute and command corrective signals. We implement these algorithms entirely on the data plane on Netronome Agilio SmartNICs. “pose correction” is placed at the edge switch connected to an industrial robot gripping a tool.
The round trip between transmitting force sensor array readings to the edge switch and receiving correct tip coordinates at the robot is shown to be less than 100µs. “tremor suppression” is placed at the edge switch connected to the operator. It suppresses physiological tremors, which improves the application’s performance and also reduces the network load up to 99.9%. Our EdgeP4 framework allows edge intelligence modules to seamlessly switch between the algorithms based on the tasks being executed by devices connected to their ports.

Speaker
Deepak Choudhary is currently a master’s student and a research assistant at Aalto University, Finland. His research interests primarily lie in Systems and Networking, specifically in software-defined networking and programmable data planes. Previously, he spent 2.5 years as a research assistant at the Indian Institute of Science (IISc). His work there focused on developing a P4-programmable Time-Sensitive Networking (TSN) switch and testing them on wide-area network testbeds.

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