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DTEND;TZID=UTC:20250806T080000
DTSTAMP:20260422T213256
CREATED:20250912T220305Z
LAST-MODIFIED:20250915T225142Z
UID:10000129-1754467200-1754467200@p4.org
SUMMARY:P4 Developer Days - Gateway Use Case Architecture for Network Applications
DESCRIPTION:Date: August 6\, 2025Time: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES\nAbstract \nNetwork applications demand ever-increasing performance and flexibility. Mapping P4 programs directly to FPGA hardware offers a powerful solution\, but the design process can be complex. This presentation demonstrates a new toolchain for efficiently mapping P4 programs to Altera FPGAs\, significantly accelerating gateway applications. Presentation leads attendees through the complete flow\, from high-level P4 specification down to a fully synthesized FPGA design using a practical gateway example. Attendees will learn how this toolchain leverages p4 language capabilities to map the user application into FPGA. This session is ideal for network architects and hardware engineers seeking to leverage the power of P4 and FPGA acceleration for next-generation network applications. \nSpeaker\nPavel Benacek is Technical Lead at Altera with more than 12 years of experience in networking technology from research and industry. He is mainly working on hardware/software co-designs and high-level synthesis topics. He holds the Ph.D. at the Czech Technical University in Prague where he was working on theory of P4 language mapping to RTL design that can be synthesized to FPGA. \n 
URL:https://p4.org/event/p4-developer-days-gateway-use-case-architecture-for-network-applications/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250820T090000
DTEND;TZID=UTC:20250820T090000
DTSTAMP:20260422T213256
CREATED:20250912T220316Z
LAST-MODIFIED:20250915T184729Z
UID:10000132-1755680400-1755680400@p4.org
SUMMARY:P4 Developer Days - Detecting Stragglers in Programmable Data Plane
DESCRIPTION:Date: August 20\, 2025Time 9:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nFlow scheduling mechanisms in modern datacenters aim to reduce flow completion time (FCT). However\, scheduling mechanisms that operate without prior knowledge\, such as PIAS\, or with imprecise flow information like QClimb\, can inadvertently introduce stragglers–packets within a flow that experience significantly higher queueing delays than others. These stragglers can lead to prolonged FCT\, undermining the goals of flow scheduling. In this talk\, we present StragFlow\, a data-plane tool for straggler detection. We implemented StragFlow in P4 using 740 lines of code. We evaluated StragFlow using real-world network traces and demonstrate that it can effectively detect stragglers across different scheduling schemes and various link conditions. Our results show that StragFlow can provide valuable insights into straggler distribution\, helping operators diagnose and mitigate flow scheduling issues to improve overall network performance. \nSpeaker\nRiz Maulana is a PhD Candidate within IRIS Cluster in the Department of Mathematics and Computer Science at Eindhoven University of Technology\, The Netherlands. His research interest includes programmable data plane\, probabilistic data structures\, and network monitoring. \n 
URL:https://p4.org/event/p4-developer-days-detecting-stragglers-in-programmable-data-plane/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250910T160000
DTEND;TZID=UTC:20250910T160000
DTSTAMP:20260422T213256
CREATED:20250912T220323Z
LAST-MODIFIED:20250919T172457Z
UID:10000150-1757520000-1757520000@p4.org
SUMMARY:P4 Developer Days - Mechanizing the P4 Language Specification with P4-SpecTec
DESCRIPTION:Date:  September 10th 4:00pm PST | September 11th – 8:00am KST \nVIEW VIDEO\nVIEW SLIDES \nAbstract\nThe P4 language has four main representations of its syntax and semantics: the official specification\, formalizations\, implementations\, and a test suite. While the four representations are intended to consistently define the P4 language\, they often diverge\, as each is managed by different parties and evolves at a different pace. This lack of alignment complicates both specification evolution and compiler maintenance. \n\n\nTo address this challenge\, we present P4-SpecTec\, a mechanized specification infrastructure for the P4 language. Inspired by successful language mechanization frameworks such as Wasm-SpecTec for WebAssembly and ESMeta for JavaScript\, P4-SpecTec introduces a formal\, complete\, and mechanized P4 language definition. From this single source of truth — the mechanized specification — we aim to generate multiple backends\, such as a type checker\, interpreter\, test suite\, and specification document\, in a consistent and automated manner. \nP4-SpecTec is an ongoing project\, where we currently mechanized the P4 type system. Notably\, our mechanized type system is executable. That is\, the typing rules can be executed\, acting as a P4 type checker. Our mechanized specification passes more than 97% of the applicable tests in the p4c test suite. This process already revealed inconsistencies and underspecified behaviors in both the P4 specification and its reference compiler. Based on the mechanized model\, we further developed a negative test generation technique that automatically produces ill-typed P4 programs that trigger subtle and diverse ill-typed conditions in the P4 type system. This approach has uncovered 11 compiler bugs and 12 soundness issues in the p4c frontend. \nThis talk introduces the design of P4-SpecTec\, current progress\, and long-term vision for a more robust and consistent P4 language ecosystem. \nSpeaker\nJaehyun Lee is a graduate student in the Programming Language Research Group at KAIST\, advised by Sukyoung Ryu. His research focuses on mechanizing programming language definitions to improve their reliability and precision. He leads the P4-SpecTec project\, which is a mechanized specification infrastructure for P4. Previously\, he contributed to the Wasm-SpecTec project\, now part of the official WebAssembly specification authoring toolchain. As part of that effort\, he co-authored the paper “Bringing the WebAssembly Standard Up to Speed with SpecTec”\, presented at PLDI 2024. His goal is to make language specifications reliable and better aligned with the needs of the developer community.
URL:https://p4.org/event/p4-developer-days-mechanizing-the-p4-language-specification-with-p4-spectec/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250917T080000
DTEND;TZID=UTC:20250917T080000
DTSTAMP:20260422T213256
CREATED:20250912T220322Z
LAST-MODIFIED:20250919T175701Z
UID:10000138-1758096000-1758096000@p4.org
SUMMARY:2025 P4 GSoC Wrap-up
DESCRIPTION:Date: September 17\, 2025\nTime: 8:00am Pacific \nThe wrap-up session highlights results of the projects hosted by The P4 Language Consortium during Google Summer of Code (GSoC) 2025. In its second consecutive year of participation\, we are pleased to share the results from each of the projects. During this session\, contributors will present their work\, share key outcomes\, and participate in a live Q&A. \nOfficial GSoC 2025 Profile: The P4 Language Consortium \nVIEW VIDEO \nAgenda \n\nOpening – Bili Dong\, Google \nP4 GSoC project presentation + discussion:\n\nBMv2 with All Possible Output Packets – Xiyu Hao\, New York University\nP4Sim Control Plane Enhancement – Vineet Goel\, Indian Institure of Technology Roorkee\nAccelerating OVS with Gigaflow: A Smart Cache for SmartNICs – Advay Singh\, University of Michigan\nSpliDT: Scaling Stateful Decision Tree Algorithms in P4 – Sankalp Jha\, Ajay Kumar Garg Engineering College\n\n\n\n  \n 
URL:https://p4.org/event/2025-p4-gsoc-wrap-up/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250925T080000
DTEND;TZID=UTC:20250925T080000
DTSTAMP:20260422T213256
CREATED:20250912T220305Z
LAST-MODIFIED:20250930T162043Z
UID:10000130-1758787200-1758787200@p4.org
SUMMARY:P4 Developer Days - From Semantics to Software: Building a Verification Ecosystem for P4 using HOL4P4
DESCRIPTION:P4 Developer Days webinar\, “From Semantics to Software: Building a Verification Ecosystem for P4 using HOL4P4”\nDate: September 25\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO\nVIEW SLIDES \nAbstract\nWe present a comprehensive formal verification ecosystem for the P4 network programming language\, built upon HOL4P4\, an abstract model of P4 execution embedded in the interactive theorem prover HOL4. The HOL4P4 formalization provides a semantics and a corresponding type system with formally verified progress\, preservation\, and type-soundness theorems. In addition\, it has been validated using a test suite from the P4 reference implementation. \nFrom this robust semantic foundation\, we have developed multiple practical verification tools. Our proof-producing symbolic execution engine enables functional correctness verification of entire real-world P4 programs\, with all results mechanically verified against the HOL4P4 semantics. Additionally\, we present a formally verified P4 software switch that maintains correctness guarantees from source to binary by leveraging both HOL4P4 and the verified CakeML compiler. This switch integrates seamlessly with existing network testing frameworks like Mininet while demonstrating decent performance compared to existing similar solutions.\n \nTogether\, these contributions demonstrate how rigorous formalization can serve as the foundation for a complete ecosystem of verification tools\, bridging the gap between theoretical guarantees and practical network development while meeting the growing demand for formal assurances in critical network infrastructure. \nSpeaker\nDidrik Lundberg combines academic research as a PhD candidate at KTH Royal Institute of Technology with practical engineering experience at Saab AB. He specializes in interactive theorem proving and formal verification\, particularly for low-level and network-related systems. His current focus is developing tools based on the HOL4P4 formalization of P4. \n 
URL:https://p4.org/event/p4-developer-days-from-semantics-to-software-building-a-verification-ecosystem-for-p4-using-hol4p4/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251001T090000
DTEND;TZID=UTC:20251001T090000
DTSTAMP:20260422T213256
CREATED:20250912T220316Z
LAST-MODIFIED:20251007T204714Z
UID:10000133-1759309200-1759309200@p4.org
SUMMARY:P4 Developer Days - Enabling Portable and High-Performance SmartNIC Programs with Alkali
DESCRIPTION:Date: October 1\, 2025\nTime: 9:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nProgramming SmartNICs today is notoriously difficult. NICs from different vendors—or even different generations of the same vendor—exhibit significant variation in hardware parallelism\, memory hierarchies\, and interconnects. As a result\, porting programs across NICs is labor-intensive and requires extensive manual refactoring to meet performance expectations on each target. \nIn this presentation\, we will present the demo and design of Alkali\, a SmartNIC compilation framework that enables developers to write target-independent programs\, while the compiler automatically handles cross-NIC porting and performance tuning. Alkali achieves this by: (1) introducing a novel intermediate representation (IR) that supports building a reusable and extensible compiler across diverse NICs\, and (2) developing an optimization algorithm that automatically transforms and parallelizes programs based on the target NIC’s hardware characteristics. \nAlkali is built on the MLIR infrastructure and is fully open source (https://github.com/utnslab/Alkali). It currently supports four distinct NIC backends and continues to grow\, including future support for P4 as part of an effort to make SmartNIC programming more portable and productive. \nSpeakers\nJiaxin Lin is an incoming assistant professor at Cornell University. She received her Ph.D. from UT Austin in the summer of 2025. Her research aims to design innovative software and hardware for accelerated data center networks. She has received the Google and Meta PhD Fellowships in Computer Networking and was selected as an MIT EECS Rising Star in 2024. \n  \n \nZhiyuan Guo is a final-year PhD student at UC San Diego. His research focuses on co-designing datacenter systems and applications for resource disaggregation. He is actively extending the concept of disaggregation and cohesive design to various datacenter systems\, including remote memory\, networking accelerators\, and machine learning infrastructure. \n  \n 
URL:https://p4.org/event/p4-developer-days-enabling-portable-and-high-performance-smartnic-programs-with-alkali/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251013T120000
DTEND;TZID=UTC:20251013T153000
DTSTAMP:20260422T213256
CREATED:20250912T220305Z
LAST-MODIFIED:20251119T000559Z
UID:10000131-1760356800-1760369400@p4.org
SUMMARY:2025 P4 Workshop
DESCRIPTION:October 13th\, Noon – 3:30pm (in-person) – San Jose Convention Center\, Lower Level\, Room LL21B \nThe P4 Workshop event is an opportunity for the P4 ecosystem to share knowledge\, insights and experiences across the broader community and to facilitate collaboration. This year the workshop will be a hybrid event and feature both in-person and pre-recorded content. The in-person portion of the workshop will take place on October 13th in conjunction with the 2025 OCP Global Summit at the San Jose Convention Center in San Jose\, California. \nIn addition\, a P4 booth will be in the OCP Global Summit exhibit hall – make sure and stop by to talk with community members and learn about P4\, how its used and how to participate. Don’t miss a demo – “Gigaflow: Pipeline-Aware Caching in Virtual Switches with P4”. \nP4 Workshop Agenda (October 13th – noon – 3:30pm)\n\nWelcome – Fernando Ramos\nGeneral Chair 2025 P4 Workshop\nView Video | View Slides\nKEYNOTE: Mina Tahmasbi Arashloo – “High-Level and Target-Agnostic Transport Programs”\nAssistant Professor Canada Research Chair in Minimizing Human Error in Modern Networks Cheriton School of Computer Science\, University of Waterloo\nAbstract: Over the past two decades\, programming abstractios for packet processing have gained widespread adoption. These abstractions enable network operators to specify packet processing logic in high-level\, domain-specific languages that are independent of the underlying hardware architecture of packet processing nodes. This approach has unlocked numerous benefits\, including compiler-driven generation of efficient low-level implementations\, portability across diverse execution environments\, and automated testing and verification. Most existing abstractions\, however\, primarily focus on L2/L3 packet processing. In this talk\, we highlight the need for new programming abstractions that capture the complexities of network mechanisms essential for quality of service\, specifically transport protocols.\nView Video | View Slides\nVictor Rios – “DVaaS Detective: The Case of the Failing Tests”\nSoftware Engineer\, Google\nView Video | View Slides\nAnand Sridharan – “Cisco Silicon One: Unifying Network Forwarding with P4 Programmability”\nDistinguished Engineer\, Cisco\nView Video | View Slides\nBREAK\nTom Herbert – “Unifying P4 with eBPF and DPDK via XDP2”\nCEO\, XDPnet\nView Video | View Slides\nDebashis Chatterjee – “New Dawn of P4”\nSenior Director of Engineering\, Intel\nView Video | View Slides\nFabian Ruffy | Vladimir Gurevich – “XASM: A Foundation to Program the X2 with P4”\nSoftware Architect | Customer Solutions Architect\, XSight Labs\nView Video | View Slides\nKEYNOTE: Krishna Doddapaneni – “Using P4 NICs for Resilient Scale-out GPU Interconnect”\nCorporate Vice President\, AMD Pensando\nAbstract: AI transports demand hardware-based solution for low latency\, high throughput GPU interconnects. P4 seems a perfect match for demanding datapath transport enabled on programmable NIC for scale-out Ethernet fabrics. The industry is standardizing packet processing\, memory transfers\, message processing\, reliability\, multipathing\, etc. over the last few years. And we are at the beginning of building and standardizing these solutions. As network components multiplies — from cables and NICs to switches and transceivers\, failures become an inevitability. Chasing a myth of perfect reliability\, a more practical approach is to design a programmable network that anticipates and handles these failures gracefully. \n\nThis talk discusses how AMD leverages the P4 to build a robust solution that overcomes network failures\, implementing a multi-plane architecture and advanced failure-handling mechanisms. How P4 capabilities demonstrate network data plane programmability is a foundational requirement in today’s demanding and unforgiving AI environments.\nView Video | View Slides\n\nAndy Fingerhut – P4 Workshop Wrap-up\nPrincipal Engineer\, Cisco\n\nP4 Workshop Pre-Recorded Talks\n\nEric Campbell – “When P4 Isn’t Enough: Specifying The Control Interface”\nPostdoctoral Research Fellow\, UT Austin\nView Video | View Slides\nMehmet Emin Sahin – “High-Accuracy Updatable Bloom Filters for Robust Network Security in Programmable Networks”\nSystems and Network Administrator\, The Scientific and Technological Research Council of Turkiye\nView Video | View Slides\nMirek Walukiewicz – “Virtual IP Load Balancer using P4”\nPrincipal Engineer\, Altera\nView Video | View Slides\nPhani Suresh Paladugu – “Enabling Programmable Performance: Memory and Interconnect Innovation for AI-Centric Data Planes”\nExecutive Director – Product Management\, Synopsys\nView Video | View Slides\nJitesh Sreedharan Nambiar – “AI‑Enabled BOM Lifecycle for P4‑Programmable Infrastructure Reliability”\nBE Graduate\, Mumbai University\nView Video | View Slides\nMohammad Firas Sada – “Cross-Federated P4 Research Testbed for Wide-Area Programmable Networking Experiments”\nData Science Research Specialist\, San Diego Supercomputer Center\nView Video | View Slides\nShaan Nagy | Ali Kheradmand – “Automated Switch Validation with Path-Complete Testing at Scale”\nPhD Student\, UCSD | Senior Software Engineer\, Google\nView Video | View Slides\nAmith Gspn – “Real-Time Encrypted Traffic Classification with P4 and DPDK”\nGraduate Student Assistant and PhD Student\, University of South Carolina\nView Video | View Slides\n\nP4 Demo\nAdvay Singh | Ali Imran | Muhammad Shahbaz – “Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern SmartNICs”\nResearch Assistant | Graduate Student Research Assistant |  Assistant Professor EECS – Computer Science and Engineering\, University of Michigan\nView Demo \nGeneral Chair\nFernando Ramos\, University of Lisbon \nProgram Committee\nAmedeo Sapio\, NVIDIA\nAndy Fingerhut\, Cisco\nBen Pfaff\, Feldera\nChris Sommers\, KeySight\nGianni Antichi\, Politecnico di Milano & Queen Mary University of London\nJonathan DiLorenzo\, Google\nMario Baldi\, NVIDIA\nMuhammad Shahbaz\, University of Michigan\nVladimir Gurevich\, P4ica \nAll attendees and participants are expected to behave in accordance with professional standards and the Linux Foundation Events Code of Conduct – for more information\, see the full Code here.
URL:https://p4.org/event/2025-p4-workshop/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251029T080000
DTEND;TZID=UTC:20251029T080000
DTSTAMP:20260422T213256
CREATED:20250912T220317Z
LAST-MODIFIED:20251104T173524Z
UID:10000135-1761724800-1761724800@p4.org
SUMMARY:P4 Developer Days - P4sim: Protocol-Independent Packet Processors in ns-3
DESCRIPTION:P4 Developer Days webinar\, “P4sim: Protocol-Independent Packet Processors in ns-3”\nDate: October 29\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nNetwork simulation plays a crucial role in evaluating new architectures\, protocols\, and algorithms before deployment. While ns-3 is one of the most widely used discrete-event network simulators\, it lacks native support for programmable data plane behaviors described in P4. P4sim addresses this gap by integrating P4’s protocol-independent\, table-driven packet processing model into the ns-3 simulation framework. This talk introduces the architecture and capabilities of P4sim\, demonstrates how developers can prototype and test P4 programs in simulation environments\, and presents example use cases such as custom switching logic and in-band telemetry. Attendees will learn about the architecture and design of P4sim\, which supports P4 architectures like V1Model\, PSA\, and PNA. The talk highlights its integration with ns-3 and showcases practical use cases. P4sim enables early development and testing of P4 programs without hardware\, making it ideal for researchers and developers in programmable networking and simulation. \nSpeaker\n \nMingyu Ma is a Ph.D. researcher at Technische Universität Dresden\, Germany\, focusing on computer networks\, programmable data planes\, and simulation platforms. Mingyu has been actively involved in bridging the gap between research prototypes and real-world deployments\, with hands-on experience in P4\, ns-3 and traffic control. He regularly contributes to academic conferences and open-source communities related to network systems and simulation. \n  \n\n 
URL:https://p4.org/event/p4-developer-days-p4sim-protocol-independent-packet-processors-in-ns-3/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251112T080000
DTEND;TZID=UTC:20251112T080000
DTSTAMP:20260422T213256
CREATED:20250912T220317Z
LAST-MODIFIED:20251119T163005Z
UID:10000134-1762934400-1762934400@p4.org
SUMMARY:P4 Developer Days - AR/CG Network Traffic Classification in Programmable Dataplane
DESCRIPTION:P4 Developer Days webinar\, “AR/CG Network Traffic Classification in Programmable Dataplane”\nDate: November 12\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nIn this presentation\, we explore the importance of classifying AR/CG traffic directly within the network device to enable low-latency\, intelligent forwarding. We outline the end-to-end process of feature extraction and deployment within a programmable data plane\, focusing on how key traffic features are computed and mirrored in P4-enabled switches. We also discuss the training of machine learning models tailored for the P4 data plane and their use in online pattern matching. Finally\, we introduce our key contributions\, including the extracted features\, developed codebase\, and publicly available repositories. \nSpeaker\nAlireza Shirmarz received his B.Sc. in Computer Engineering from Shahed University in 2009 and his M.Sc. in Network Engineering from Amirkabir University of Technology (Tehran Polytechnic) in 2014. He earned his Ph.D. in Computer Engineering from IAU-Tehran North Branch in 2020. Since 2014\, he has been actively teaching undergraduate courses in computer science and engineering and has been involved in graduate and Ph.D. supervision since 2020. \nHis research focuses on the intersection of networking and AI/ML\, particularly in optimizing Quality of Experience (QoE) for real-time and interactive applications in future networks\, including 6G. He specializes in intelligent data plane solutions\, SDN architectures\, and QoS/QoE management. Currently\, he is a Postdoctoral Researcher at UFSCar\, advancing AI/ML applications in networking. \n 
URL:https://p4.org/event/p4-developer-days-ar-cg-network-traffic-classification-in-programmable-dataplane/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251119T080000
DTEND;TZID=UTC:20251119T080000
DTSTAMP:20260422T213256
CREATED:20250912T220322Z
LAST-MODIFIED:20251202T154731Z
UID:10000137-1763539200-1763539200@p4.org
SUMMARY:P4 Developer Days - Implementation of Periodic Behavior with P4: Challenges and Solutions on Intel Tofino with Application in Time-Sensitive Networking (TSN)
DESCRIPTION:P4 Developer Days webinar\, “Implementation of Periodic Behavior with P4: Challenges and Solutions on Intel Tofino with Application in Time-Sensitive Networking (TSN)” \nView Slides \nView Video \nAbstract\nImplementing periodic time behavior in hardware data planes is challenging due to limited arithmetic capabilities such as the lack of modulo operations\, restricted timestamp precision\, and resource constraints. This talk presents a general mechanism for implementing periodic time logic in P4\, i.e.\, enabling data plane behavior that repeats in fixed time intervals\, applicable to a broad range of time-aware applications. The mechanism enables periodic packet matching by mapping absolute timestamps to relative positions within a hyperperiod. To emulate hyperperiod boundaries\, we leverage the switch’s internal packet generator to generate periodic trigger packets that act as time anchors for computing relative timestamps. \n\nAs a concrete use case\, we apply this mechanism to implement Per-Stream Filtering and Policing (PSFP) as defined in IEEE 802.1Qci. Our implementation on Intel Tofino™ hardware demonstrates reliable time-based gating at line rate. Finally\, we discuss how this periodicity mechanism can be extended to implement additional time-sensitive features such as the Time-Aware Shaper (TAS)\, offering a scalable foundation for deterministic network behavior in P4-based systems.\n\n\nSpeaker\nFabian Ihle received his bachelor’s (2021) and master’s degrees (2023) in computer science at the University of Tuebingen. Afterwards\, he joined the communication networks research group of Prof. Dr. Habil Michael Menth as a Ph.D. student. His research interests include software-defined networking\, P4-based data plane programming\, resilience\, and Time-Sensitive Networking (TSN). \n\n 
URL:https://p4.org/event/p4-developer-days-implementation-of-periodic-behavior-with-p4-challenges-and-solutions-on-intel-tofino-with-application-in-time-sensitive-networking-tsn/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251203T080000
DTEND;TZID=UTC:20251203T080000
DTSTAMP:20260422T213256
CREATED:20250912T220324Z
LAST-MODIFIED:20251204T193414Z
UID:10000141-1764748800-1764748800@p4.org
SUMMARY:P4 Developer Days - QuIP: A P4 Quantum Internet Protocol Prototyping Framework
DESCRIPTION:P4 Developer Days webinar\, “QuIP: A P4 Quantum Internet Protocol Prototyping Framework” \nView Slides \nView Video \nAbstract\n\n\nQuantum entanglement is so fundamentally different from a network packet that several quantum network stacks have been proposed; one of which has even been experimentally demonstrated. Several simulators have also been developed to make up for limited hardware availability\, and which facilitate the design and evaluation of quantum network protocols. However\, the lack of shared tooling and community-agreed node architectures has resulted in protocol implementations that are tightly coupled to their simulators. Besides limiting their reusability between different simulators\, it also makes building upon prior results and simulations difficult. To address this problem\, we have developed QuIP: a P4-based Quantum Internet Protocol prototyping framework for quantum network protocol design. QuIP is a framework for designing and implementing quantum network protocols in a platform-agnostic fashion. It achieves this by providing the means to flexibly\, but rigorously\, define device architectures against which quantum network protocols can be implemented in the network programming language P416. QuIP also comes with the necessary tooling to enable their execution in existing quantum network simulators. We demonstrate its use by showcasing V1Quantum\, a completely new device architecture\, implementing a link- and network-layer protocol\, and simulating it in the existing simulator NetSquid. \nSpeaker\nWojciech Kozlowski is the Quantum Communication Topic Lead at SURF. He completed his MSci in Theoretical Quantum Physics at the University of Cambridge and his PhD in Atomic and Laser Physics at the University of Oxford. Since then\, Wojciech has been involved with networks\, both classical and quantum. After his PhD he joined Metaswitch in London where he worked as a software engineer developing (classical) control planes. In 2019\, Wojciech moved to the Netherlands where he worked  as a postdoc and later quantum network engineer at the TU Delft before joining SURF in 2024.
URL:https://p4.org/event/p4-developer-days-quip-a-p4-quantum-internet-protocol-prototyping-framework/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251210T080000
DTEND;TZID=UTC:20251210T080000
DTSTAMP:20260422T213256
CREATED:20250912T220323Z
LAST-MODIFIED:20251212T154953Z
UID:10000140-1765353600-1765353600@p4.org
SUMMARY:P4 Developer Days - Programmable Hardware Emulation Environment for Realistic and Scalable Network Testing
DESCRIPTION:P4 Developer Days: “Programmable Hardware Emulation Environment for Realistic and Scalable Network Testing” \nView Slides \nView Video \nAbstract\nNetwork emulators are essential for testing and validating new networking solutions before deployment. In this presentation\, we will showcase a hardware-based emulation framework that brings programmable switches and SmartNIC awareness to network experimentation. Our environment enables realistic and scalable evaluation of offloading\, host interaction\, and in-network processing. Through a simple API\, researchers can define and deploy multi-switch\, multi-host topologies; configure diverse link characteristics (e.g.\, bandwidth\, latency\, packet loss); and generate realistic traffic patterns. Finally\, we validate the environment using multiple state-of-the-art scenarios\, assessing robustness by reproducing and extending prior experiments across an expanded evaluation space. \nSpeakers\nFabricio Rodriguez received the M.Sc. and Ph.D. degrees in Electrical Engineering from the Universidade Estadual de Campinas in 2018 and 2024\, respectively. He was a researcher with the Information Networking Technologies Research Innovation Group (INTRIG)\, participating in projects with Ericsson\, Padtec\, and RNP. He is currently a Research Scientist at Telefónica Research\, Spain. His research interests include programmable networks\, in-network applications\, security\, and network performance. \n  \nFrancisco Vogt received the bachelor’s degree in computer science from the Federal University of Pampa and the master’s degree in computer engineering from the Universidade Estadual de Campinas\, Brazil\, where he is currently pursuing the Ph.D. degree in electrical engineering. He is currently a Visiting Researcher with the University of Amsterdam and works with the Multiscale Networked Systems (MNS) Research Group. He is involved as a Researcher with Ericsson on the project “SMARTNESS 2030: SMART NEtworks and ServiceS for 2030.” His research interests include programmable networks\, network monitoring\, network function offloading\, and network testing. \nRegister to attend this webinar! \n 
URL:https://p4.org/event/p4-developer-days-programmable-hardware-emulation-environment-for-realistic-and-scalable-network-testing/
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BEGIN:VEVENT
DTSTART;TZID=UTC:20260121T080000
DTEND;TZID=UTC:20260121T080000
DTSTAMP:20260422T213256
CREATED:20250912T220334Z
LAST-MODIFIED:20260122T175551Z
UID:10000142-1768982400-1768982400@p4.org
SUMMARY:P4 Developer Days - In-Network Inference with P4: From Stateless to Hybrid Approaches
DESCRIPTION:P4 Developer Days webinar\, “In-Network Inference with P4: From Stateless to Hybrid Approaches” \nView Slides \nView Video \nAbstract\nIn-network machine learning (ML) techniques employ the P4 language to embed trained ML models directly into programmable network data planes. This has enabled novel applications in network security\, routing optimization\, and traffic classification\, amongst others. This presentation charts the evolution of these techniques\, starting with stateless\, packet-level inference models like Henna. It then explores the shift to stateful\, flow-level approaches as demonstrated in Flowrest. The talk culminates with Jewel\, a novel hybrid system that performs joint packet and flow-level inference for improved accuracy and efficiency. This journey from stateless to hybrid methodologies highlights the advancements and trade-offs in building intelligent\, high-performance\, and ML-empowered networks with P4.\n\n \nSpeaker\nAristide Akem is a Lecturer in Computer Science within the Cyberphysical Systems Group in the School of Electronics and Computer Science at the University of Southampton. Before joining Southampton\, he was a postdoctoral researcher in the Computing Infrastructure Group at the University of Oxford. His research spans machine learning\, network programming with P4\, and mobile networking\, with applications in network security\, IoT\, and energy. He earned his PhD from Universidad Carlos III de Madrid and IMDEA Networks Institute\, following a Master of Science in Electrical and Computer Engineering from Carnegie Mellon University Africa\, and a Master’s in Telecommunications Engineering from the University of Yaounde I.
URL:https://p4.org/event/p4-developer-days-in-network-inference-with-p4-from-stateless-to-hybrid-approaches/
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BEGIN:VEVENT
DTSTART;TZID=UTC:20260204T080000
DTEND;TZID=UTC:20260204T090000
DTSTAMP:20260422T213256
CREATED:20251007T163320Z
LAST-MODIFIED:20260213T141052Z
UID:10000154-1770192000-1770195600@p4.org
SUMMARY:P4 Developer Days - Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA based SmartNICs
DESCRIPTION:In case you missed it\, you can now view the recording of this P4 Developer Days webinar\, “Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA-based SmartNICs”\n\n\n\nView Video\nView Slides\n\nAbstract\nThe exponential growth of cloud-native services\, 5G connectivity\, and data-intensive applications is driving unprecedented demand for high-throughput and flexible packet processing. Traditional fixed-function ASIC solutions\, while performant\, lack the adaptability to address emerging tunnelling protocols\, dynamic QoS enforcement\, and evolving custom workloads. P4\, an open and protocol-independent programming language for the data plane\, directly addresses these limitations by enabling developers to rapidly define and deploy advanced packet pipelines without RTL complexity. By combining FPGA Vendors P4 Compilers like Altera’s P4 Suite with iW-Fibre SmartNICs\, operators can synthesize programmable pipelines that sustain line-rate performance while remaining fully adaptable. \nDemonstration of the use cases – including checksum verification\, IP-in-IP tunnelling\, VXLAN encapsulation/decapsulation\, and standards-based QoS metering—illustrate how P4 empowers service providers and data centers to stay agile\, scalable\, and future-ready. \nSpeaker\nChethan T V is an Electronics an Communications Engineer possessing diverse experience in embedded industry as a digital design engineer with extensive expertise in FPGA design flow and SoC lifecycle. With strong project management skills\, he has led various challenging projects from conceptualization stage to execution and delivered successful products in the field of defense\, video\, military & commercial sectors. He is an Associate Director\, FPGA BU\, iWave Global – leading the Smart-NIC division from the ground up\, building a high-performing team\, and driving strategic projects in next-generation networking.
URL:https://p4.org/event/p4-developer-days-programmable-data-planes-for-the-cloud-era-harnessing-p4-on-fpga-based-smartnics/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260304T080000
DTEND;TZID=America/Vancouver:20260304T090000
DTSTAMP:20260422T213256
CREATED:20251024T165254Z
LAST-MODIFIED:20260306T175333Z
UID:10000155-1772611200-1772614800@p4.org
SUMMARY:P4 Developer Days - P4Muse (P4 Modularity and Unification for Seamless Extensibility)
DESCRIPTION:Register to attend this P4 Developer Days webinar\, “P4Muse (P4 Modularity and Unification for Seamless Extensibility”\nDate: March 4\, 2026\nTime: 8:00am Pacific \nSlides (PDF) | Watch Recording \nAbstract\n\n\n\nDomain-specific programming languages such as P4 enable flexible and high-performance packet processing in programmable network data planes. However\, most P4 programs remain monolithic\, limiting the development of modular and reusable protocols and libraries. Introducing modularity to P4 has been challenging because existing approaches—such as trans-compilers and virtualization—operate outside the P4 language and compiler\, reducing backward compatibility and extensibility. P4Muse (P4 Modularity and Unification for Seamless Extensibility) addresses this challenge by introducing a compiler-managed approach to modularity within the P4C compiler. Without requiring any new syntax or annotations\, P4Muse introduces new compiler passes for automatic code merging\, enabling modular design\, reuse\, and seamless integration of complex network functionalities. Our results show that P4Muse effectively supports modular P4 program development without altering existing P4 syntax\, providing a robust solution that significantly improves code reusability\, flexibility\, and extensibility while maintaining backward compatibility. \n\n\n\n\nSpeakers\nMohsen Rahmati is a Ph.D. candidate in Computer Engineering at Polytechnique Montréal\, supervised by Professors Yvon Savaria\, François-Raymond Boyer\, and Jean-Pierre David. His research focuses on compiler design for programmable networks\, emphasizing modularity and reusability in the P4 language. He is the creator of P4Muse\, a compiler-managed modularity framework (accepted in IEEE Access\, 2025)\, and P4O2\, an object-oriented-inspired modularity in P4 currently under review at IEEE Access. \n\n  \nFrançois-Raymond Boyer received B.Sc. and Ph.D. degrees in computer science from Université de Montréal\, Montreal\, QC\, Canada\, in 1996 and 2001\, respectively. Since 2001\, he has been with Polytechnique Montréal\, Montréal\, where he is currently a Professor with the Department of Computer and Software Engineering. He has authored or co-authored more than 30 conference and journal papers. His current research interests include microelectronics\, performance optimization\, parallelizing compilers\, digital audio\, and body motion capture. He is a member of Regroupement Stratégique en Microélectronique du Québec\, Groupe de Recherche en Microélectronique et Microsystèmes\, and Observatoire Interdisciplinaire de Création et de Recherche en Musique.
URL:https://p4.org/event/p4-developer-days-p4muse-p4-modularity-and-unification-for-seamless-extensibility/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=UTC:20260319T080000
DTEND;TZID=UTC:20260319T090000
DTSTAMP:20260422T213256
CREATED:20251117T170038Z
LAST-MODIFIED:20260320T115620Z
UID:10000156-1773907200-1773910800@p4.org
SUMMARY:P4 Developer Days - SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate
DESCRIPTION:Register to attend this P4 Developer Days webinar\, “SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate”\nMarch 19 at 11 am ET/4 pm CET \nSlides (PDF) || Watch Recording \n\n\n\nAbstract\nMachine learning is increasingly used in programmable data planes\, such as switches and smartNICs\, to enable real-time traffic analysis and security monitoring at line rate. Decision trees (DTs) are particularly well-suited for these tasks due to their interpretability and compatibility with the Reconfigurable Match-Action Table (RMT) architecture. However\, current DT implementations require collecting all features upfront\, which limits scalability and accuracy due to constrained data plane resources. This paper introduces SpliDT\, a scalable framework that reimagines DT deployment as a partitioned inference problem over a sliding window of packets. \nBy dividing inference into sequential subtrees—each using its own set of top-k features—SpliDT supports more stateful features without exceeding hardware limits. An in-band control channel manages transitions between subtrees and reuses match keys and registers across partitions\, implemented using P4 for packet recirculation and control-plane coordination. This design allows physical resources to be shared efficiently while maintaining line-rate processing. To maximize accuracy and scalability\, SpliDT employs a custom training and design-space-exploration (DSE) workflow that jointly optimizes feature allocation\, tree depth\, and partitioning. Evaluations show that SpliDT supports up to 5x more features\, scales to millions of flows\, and outperforms baselines\, with low overhead and minimal time-to-detection (TTD). \n\n\nSpeaker\nMurayyiam Parvez is a Ph.D. candidate in the Department of Computer Science at Purdue University\, advised by Professor Muhammad Shahbaz and Professor Sonia Fahmy. Her research focuses on designing the next generation of hybrid software–hardware abstractions and architectures for emerging network security and machine learning applications\, with an emphasis on leveraging programmable switches to enable high-performance\, in-network intelligence. \n\nRegister to attend this webinar!
URL:https://p4.org/event/p4-developer-days-splidt-partitioned-decision-trees-for-scalable-stateful-inference-at-line-rate/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260430T080000
DTEND;TZID=America/Vancouver:20260430T090000
DTSTAMP:20260422T213256
CREATED:20260403T165242Z
LAST-MODIFIED:20260403T165346Z
UID:10000158-1777536000-1777539600@p4.org
SUMMARY:P4 Developer Days – OpenDesc: Describing NIC-Host Interfaces
DESCRIPTION:Register to attend this P4 Developer Day webinar on April 30 at 11 am ET/5 pm CET \nOpenDesc: Describing NIC-Host Interfaces\n\n\nAbstract\nModern NIC hardware is increasingly expressive\, yet host software remains shackled to static\, device-specific descriptors and ad-hoc glue layers. We present OpenDesc\, a framework that leverages P4 to define the interface between host and NIC. By treating software intent and hardware capabilities as negotiable P4 programs\, OpenDesc automatically compiles minimalist\, application-specific driver datapaths for metadata. This approach eliminates the “lowest common denominator” bottleneck\, enabling seamless metadata exchange and hardware-software co-design across heterogeneous NIC architectures. \nSpeaker\nSeyyidahmed is a systems researcher at imec. His research interests include the co-design of programmable hardware and high-performance networking stacks\, with a focus on improving the flexibility\, programmability\, and efficiency of modern networked systems. \n\n\nRegister to attend this virtual & free event
URL:https://p4.org/event/devday-opendesc/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260513T080000
DTEND;TZID=America/Vancouver:20260513T090000
DTSTAMP:20260422T213256
CREATED:20260407T160827Z
LAST-MODIFIED:20260409T172827Z
UID:10000159-1778659200-1778662800@p4.org
SUMMARY:P4 Developer Days – P4TC Provisioning And Runtime Control API
DESCRIPTION:Register to attend this P4 Developer Day webinar on May 13 at 11 am ET/5 pm CET \nP4TC Provisioning And Runtime Control API\n\n\nAbstract\nThe P4TC Control APIs consist of two primary interfaces built on the netlink framework: one for provisioning P4 program manifestations in the Linux kernel and another for managing the P4 runtime. This talk focuses on the P4TC runtime\, which employs P4 annotations to link datapath constructs with the control plane. These annotations are converted by the compiler into a JSON format\, allowing runtime control applications to introspect both control and data path constructs. \nArchitecturally\, the P4TC runtime API is inspired by the REST paradigm\, employing resource-oriented paths as nouns and a refined set of verbs. The verbs follow CRUD (Create\, Read\, Update\, and Delete) principles and include specialized extensions for event publish-subscribe functionality. By using “paths” to target specific datapath objects\, the API remains agnostic regarding the nature of those objects – implying a control application does not need to change for multitudes of P4 programs. \nSpeaker\nFor more than twenty years\, Jamal Hadi Salim has been a leader in the evolution of networking and Software-Defined Networking (SDN). He is a major contributor to the Linux kernel networking subsystem and the current maintainer of the Traffic Control (tc) subsystem. Currently\, he leads the P4TC initiative\, which enables P4 programs to run directly within the Linux kernel. \nHis previous leadership roles include serving as the chair for the IETF SDN working group on Forwarding and Control Element Separation (ForCES). During his tenure\, he developed a ForCES implementation used in large-scale telecommunications and authored multiple SDN standards. Currently\, Jamal is concentrating on the performance of AI/ML\, with a specific emphasis on networking protocols and infrastructure. \n\n\nRegister to attend this virtual & free event \nFurther Reading\nWant to learn more about P4TC? Check out their blog
URL:https://p4.org/event/p4tc-may-13/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260520T080000
DTEND;TZID=America/Vancouver:20260520T090000
DTSTAMP:20260422T213256
CREATED:20260310T142654Z
LAST-MODIFIED:20260409T151432Z
UID:10000157-1779264000-1779267600@p4.org
SUMMARY:P4 Developer Days – EdgeP4: In-Network Edge Intelligence for a Tactile Cyber-Physical System Testbed Across Cities
DESCRIPTION:Register to attend this P4 Developer Day webinar on May 20 at 11 am ET/5 pm CET \nEdgeP4: In-Network Edge Intelligence for a Tactile Cyber-Physical System Testbed Across Cities\n\n\nAbstract\nTactile Internet based operations\, e.g.\, telesurgery\, rely on the human operator for end-to-end closed loop control to achieve accuracy. While feedback and control are subject to network latency and packet loss\, critical operations such as pose correction\, fiducial marking\, tremor reduction\, etc. are tasks that should be carried out automatically and thus dispensing with these feedback signals from traversing the network to the other end. We designed two edge intelligence algorithms hosted at P4 programmable end switches placed 400 km apart. These algorithms locally compute and command corrective signals. We implement these algorithms entirely on the data plane on Netronome Agilio SmartNICs. “pose correction” is placed at the edge switch connected to an industrial robot gripping a tool. \nThe round trip between transmitting force sensor array readings to the edge switch and receiving correct tip coordinates at the robot is shown to be less than 100µs. “tremor suppression” is placed at the edge switch connected to the operator. It suppresses physiological tremors\, which improves the application’s performance and also reduces the network load up to 99.9%. Our EdgeP4 framework allows edge intelligence modules to seamlessly switch between the algorithms based on the tasks being executed by devices connected to their ports. \n\nSpeaker\nDeepak Choudhary is currently a master’s student and a research assistant at Aalto University\, Finland. His research interests primarily lie in Systems and Networking\, specifically in software-defined networking and programmable data planes. Previously\, he spent 2.5 years as a research assistant at the Indian Institute of Science (IISc). His work there focused on developing a P4-programmable Time-Sensitive Networking (TSN) switch and testing them on wide-area network testbeds. \n\nRegister to attend this virtual & free event
URL:https://p4.org/event/edgep4-may20/
CATEGORIES:Events
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