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X-WR-CALDESC:Events for P4 - Language Consortium
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BEGIN:VEVENT
DTSTART;TZID=UTC:20251001T090000
DTEND;TZID=UTC:20251001T090000
DTSTAMP:20260417T032036
CREATED:20250912T220316Z
LAST-MODIFIED:20251007T204714Z
UID:10000133-1759309200-1759309200@p4.org
SUMMARY:P4 Developer Days - Enabling Portable and High-Performance SmartNIC Programs with Alkali
DESCRIPTION:Date: October 1\, 2025\nTime: 9:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nProgramming SmartNICs today is notoriously difficult. NICs from different vendors—or even different generations of the same vendor—exhibit significant variation in hardware parallelism\, memory hierarchies\, and interconnects. As a result\, porting programs across NICs is labor-intensive and requires extensive manual refactoring to meet performance expectations on each target. \nIn this presentation\, we will present the demo and design of Alkali\, a SmartNIC compilation framework that enables developers to write target-independent programs\, while the compiler automatically handles cross-NIC porting and performance tuning. Alkali achieves this by: (1) introducing a novel intermediate representation (IR) that supports building a reusable and extensible compiler across diverse NICs\, and (2) developing an optimization algorithm that automatically transforms and parallelizes programs based on the target NIC’s hardware characteristics. \nAlkali is built on the MLIR infrastructure and is fully open source (https://github.com/utnslab/Alkali). It currently supports four distinct NIC backends and continues to grow\, including future support for P4 as part of an effort to make SmartNIC programming more portable and productive. \nSpeakers\nJiaxin Lin is an incoming assistant professor at Cornell University. She received her Ph.D. from UT Austin in the summer of 2025. Her research aims to design innovative software and hardware for accelerated data center networks. She has received the Google and Meta PhD Fellowships in Computer Networking and was selected as an MIT EECS Rising Star in 2024. \n  \n \nZhiyuan Guo is a final-year PhD student at UC San Diego. His research focuses on co-designing datacenter systems and applications for resource disaggregation. He is actively extending the concept of disaggregation and cohesive design to various datacenter systems\, including remote memory\, networking accelerators\, and machine learning infrastructure. \n  \n 
URL:https://p4.org/event/p4-developer-days-enabling-portable-and-high-performance-smartnic-programs-with-alkali/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250925T080000
DTEND;TZID=UTC:20250925T080000
DTSTAMP:20260417T032036
CREATED:20250912T220305Z
LAST-MODIFIED:20250930T162043Z
UID:10000130-1758787200-1758787200@p4.org
SUMMARY:P4 Developer Days - From Semantics to Software: Building a Verification Ecosystem for P4 using HOL4P4
DESCRIPTION:P4 Developer Days webinar\, “From Semantics to Software: Building a Verification Ecosystem for P4 using HOL4P4”\nDate: September 25\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO\nVIEW SLIDES \nAbstract\nWe present a comprehensive formal verification ecosystem for the P4 network programming language\, built upon HOL4P4\, an abstract model of P4 execution embedded in the interactive theorem prover HOL4. The HOL4P4 formalization provides a semantics and a corresponding type system with formally verified progress\, preservation\, and type-soundness theorems. In addition\, it has been validated using a test suite from the P4 reference implementation. \nFrom this robust semantic foundation\, we have developed multiple practical verification tools. Our proof-producing symbolic execution engine enables functional correctness verification of entire real-world P4 programs\, with all results mechanically verified against the HOL4P4 semantics. Additionally\, we present a formally verified P4 software switch that maintains correctness guarantees from source to binary by leveraging both HOL4P4 and the verified CakeML compiler. This switch integrates seamlessly with existing network testing frameworks like Mininet while demonstrating decent performance compared to existing similar solutions.\n \nTogether\, these contributions demonstrate how rigorous formalization can serve as the foundation for a complete ecosystem of verification tools\, bridging the gap between theoretical guarantees and practical network development while meeting the growing demand for formal assurances in critical network infrastructure. \nSpeaker\nDidrik Lundberg combines academic research as a PhD candidate at KTH Royal Institute of Technology with practical engineering experience at Saab AB. He specializes in interactive theorem proving and formal verification\, particularly for low-level and network-related systems. His current focus is developing tools based on the HOL4P4 formalization of P4. \n 
URL:https://p4.org/event/p4-developer-days-from-semantics-to-software-building-a-verification-ecosystem-for-p4-using-hol4p4/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250917T080000
DTEND;TZID=UTC:20250917T080000
DTSTAMP:20260417T032036
CREATED:20250912T220322Z
LAST-MODIFIED:20250919T175701Z
UID:10000138-1758096000-1758096000@p4.org
SUMMARY:2025 P4 GSoC Wrap-up
DESCRIPTION:Date: September 17\, 2025\nTime: 8:00am Pacific \nThe wrap-up session highlights results of the projects hosted by The P4 Language Consortium during Google Summer of Code (GSoC) 2025. In its second consecutive year of participation\, we are pleased to share the results from each of the projects. During this session\, contributors will present their work\, share key outcomes\, and participate in a live Q&A. \nOfficial GSoC 2025 Profile: The P4 Language Consortium \nVIEW VIDEO \nAgenda \n\nOpening – Bili Dong\, Google \nP4 GSoC project presentation + discussion:\n\nBMv2 with All Possible Output Packets – Xiyu Hao\, New York University\nP4Sim Control Plane Enhancement – Vineet Goel\, Indian Institure of Technology Roorkee\nAccelerating OVS with Gigaflow: A Smart Cache for SmartNICs – Advay Singh\, University of Michigan\nSpliDT: Scaling Stateful Decision Tree Algorithms in P4 – Sankalp Jha\, Ajay Kumar Garg Engineering College\n\n\n\n  \n 
URL:https://p4.org/event/2025-p4-gsoc-wrap-up/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250910T160000
DTEND;TZID=UTC:20250910T160000
DTSTAMP:20260417T032036
CREATED:20250912T220323Z
LAST-MODIFIED:20250919T172457Z
UID:10000150-1757520000-1757520000@p4.org
SUMMARY:P4 Developer Days - Mechanizing the P4 Language Specification with P4-SpecTec
DESCRIPTION:Date:  September 10th 4:00pm PST | September 11th – 8:00am KST \nVIEW VIDEO\nVIEW SLIDES \nAbstract\nThe P4 language has four main representations of its syntax and semantics: the official specification\, formalizations\, implementations\, and a test suite. While the four representations are intended to consistently define the P4 language\, they often diverge\, as each is managed by different parties and evolves at a different pace. This lack of alignment complicates both specification evolution and compiler maintenance. \n\n\nTo address this challenge\, we present P4-SpecTec\, a mechanized specification infrastructure for the P4 language. Inspired by successful language mechanization frameworks such as Wasm-SpecTec for WebAssembly and ESMeta for JavaScript\, P4-SpecTec introduces a formal\, complete\, and mechanized P4 language definition. From this single source of truth — the mechanized specification — we aim to generate multiple backends\, such as a type checker\, interpreter\, test suite\, and specification document\, in a consistent and automated manner. \nP4-SpecTec is an ongoing project\, where we currently mechanized the P4 type system. Notably\, our mechanized type system is executable. That is\, the typing rules can be executed\, acting as a P4 type checker. Our mechanized specification passes more than 97% of the applicable tests in the p4c test suite. This process already revealed inconsistencies and underspecified behaviors in both the P4 specification and its reference compiler. Based on the mechanized model\, we further developed a negative test generation technique that automatically produces ill-typed P4 programs that trigger subtle and diverse ill-typed conditions in the P4 type system. This approach has uncovered 11 compiler bugs and 12 soundness issues in the p4c frontend. \nThis talk introduces the design of P4-SpecTec\, current progress\, and long-term vision for a more robust and consistent P4 language ecosystem. \nSpeaker\nJaehyun Lee is a graduate student in the Programming Language Research Group at KAIST\, advised by Sukyoung Ryu. His research focuses on mechanizing programming language definitions to improve their reliability and precision. He leads the P4-SpecTec project\, which is a mechanized specification infrastructure for P4. Previously\, he contributed to the Wasm-SpecTec project\, now part of the official WebAssembly specification authoring toolchain. As part of that effort\, he co-authored the paper “Bringing the WebAssembly Standard Up to Speed with SpecTec”\, presented at PLDI 2024. His goal is to make language specifications reliable and better aligned with the needs of the developer community.
URL:https://p4.org/event/p4-developer-days-mechanizing-the-p4-language-specification-with-p4-spectec/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250820T090000
DTEND;TZID=UTC:20250820T090000
DTSTAMP:20260417T032036
CREATED:20250912T220316Z
LAST-MODIFIED:20250915T184729Z
UID:10000132-1755680400-1755680400@p4.org
SUMMARY:P4 Developer Days - Detecting Stragglers in Programmable Data Plane
DESCRIPTION:Date: August 20\, 2025Time 9:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nFlow scheduling mechanisms in modern datacenters aim to reduce flow completion time (FCT). However\, scheduling mechanisms that operate without prior knowledge\, such as PIAS\, or with imprecise flow information like QClimb\, can inadvertently introduce stragglers–packets within a flow that experience significantly higher queueing delays than others. These stragglers can lead to prolonged FCT\, undermining the goals of flow scheduling. In this talk\, we present StragFlow\, a data-plane tool for straggler detection. We implemented StragFlow in P4 using 740 lines of code. We evaluated StragFlow using real-world network traces and demonstrate that it can effectively detect stragglers across different scheduling schemes and various link conditions. Our results show that StragFlow can provide valuable insights into straggler distribution\, helping operators diagnose and mitigate flow scheduling issues to improve overall network performance. \nSpeaker\nRiz Maulana is a PhD Candidate within IRIS Cluster in the Department of Mathematics and Computer Science at Eindhoven University of Technology\, The Netherlands. His research interest includes programmable data plane\, probabilistic data structures\, and network monitoring. \n 
URL:https://p4.org/event/p4-developer-days-detecting-stragglers-in-programmable-data-plane/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250806T080000
DTEND;TZID=UTC:20250806T080000
DTSTAMP:20260417T032036
CREATED:20250912T220305Z
LAST-MODIFIED:20250915T225142Z
UID:10000129-1754467200-1754467200@p4.org
SUMMARY:P4 Developer Days - Gateway Use Case Architecture for Network Applications
DESCRIPTION:Date: August 6\, 2025Time: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES\nAbstract \nNetwork applications demand ever-increasing performance and flexibility. Mapping P4 programs directly to FPGA hardware offers a powerful solution\, but the design process can be complex. This presentation demonstrates a new toolchain for efficiently mapping P4 programs to Altera FPGAs\, significantly accelerating gateway applications. Presentation leads attendees through the complete flow\, from high-level P4 specification down to a fully synthesized FPGA design using a practical gateway example. Attendees will learn how this toolchain leverages p4 language capabilities to map the user application into FPGA. This session is ideal for network architects and hardware engineers seeking to leverage the power of P4 and FPGA acceleration for next-generation network applications. \nSpeaker\nPavel Benacek is Technical Lead at Altera with more than 12 years of experience in networking technology from research and industry. He is mainly working on hardware/software co-designs and high-level synthesis topics. He holds the Ph.D. at the Czech Technical University in Prague where he was working on theory of P4 language mapping to RTL design that can be synthesized to FPGA. \n 
URL:https://p4.org/event/p4-developer-days-gateway-use-case-architecture-for-network-applications/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250709T080000
DTEND;TZID=UTC:20250709T080000
DTSTAMP:20260417T032036
CREATED:20250912T220304Z
LAST-MODIFIED:20250915T225148Z
UID:10000128-1752048000-1752048000@p4.org
SUMMARY:P4 Developer Days - P4-based AI Feature Extractor for Volumetric Firewall Use Cases
DESCRIPTION:Date: July 9\, 2025Time 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract \nUsing volumetry data is a very important feature of many firewalls from major security vendors. The changing security landscape and a need for performance and flexibility drive the use of AI/ML engines working more efficiently. The presentation shows an example of the use of P4 language to prepare a training feature and an example of an inference engine using P4 as a feature extractor for the SYN-FLOOD attack detector. The P4\, as a packet processing language\, can be used to define the network traffic-based features for AI/ML processing. The AI/ML engines can be abstracted as P4 externs. The P4 defines what packet fields are of interest in AI/ML process. Such P4 engine implementation (based on hardware or software) can also prepare/preprocess the AI/ML engine input (for example\, rate of some packets or counter selection). It can also prepare the packet-based response using AI/ML external outcome. The presentation provides an overview of some challenges\, like a lack of standardized datasets and performance requirements. \nSpeaker\nMirek Walukiewicz is a Principal Engineer at Altera with more than 32 years of experience in networking technology. He is a Solution Architect actively working with customers on various P4 applications using FPGA-like security\, packet scheduling\, clock synchronization\, and more. He drives P4 efforts inside Altera. \n 
URL:https://p4.org/event/p4-developer-days-p4-based-ai-feature-extractor-for-volumetric-firewall-use-cases/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250611T080000
DTEND;TZID=UTC:20250611T080000
DTSTAMP:20260417T032036
CREATED:20250912T220304Z
LAST-MODIFIED:20250915T225203Z
UID:10000127-1749628800-1749628800@p4.org
SUMMARY:P4 GSoC 2025 Kickoff Meeting
DESCRIPTION:Learn about the projects hosted by the P4 Project in Google Summer of Code (GSoC) 2025. Each project will be presented by the contributor. \nAgenda \n\n\n\nIntroduction – Nate Foster\nGSoC proposal presentation + discussion:\n\n\n\n\n\n\n\n\nBMv2 With All Possible Output Packets – Xiyu Hao\nP4Sim Control Plane Enhancement – Vineet Goel\nP4MLIR: MLIR-based high-level IR for P4 compilers – Xiaomin Liu\nAccelerating OVS with Gigaflow: A Smart Cache for SmartNICs – Advay Singh\nSpliDT: Scaling Stateful Decision Tree Algorithms in P4 – Sankalp Jha\n\n\n\n\n\nVIEW VIDEO \nVIEW SLIDES
URL:https://p4.org/event/p4-gsoc-2025-kickoff-meeting/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250604T080000
DTEND;TZID=UTC:20250604T080000
DTSTAMP:20260417T032036
CREATED:20250912T220259Z
LAST-MODIFIED:20250915T225237Z
UID:10000126-1749024000-1749024000@p4.org
SUMMARY:P4 Developer Days - Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern Smart NICs
DESCRIPTION:P4 Developer Days webinar\, “Pipeline-Aware Sub-Traversal Caching for Modern Smart NICs”\nDate: June 4\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nThe success of modern public/edge clouds hinges heavily on the performance of their end-host network stacks if they are to support the emerging and diverse tenants’ workloads (e.g.\, distributed training in the cloud to fast inference at the edge). Virtual Switches (vSwitches) are vital components of this stack\, providing a unified interface to enforce high-level policies on incoming packets and route them to physical interfaces\, containers\, or virtual machines. As performance demands escalate\, there has been a shift toward offloading vSwitch processing to SmartNICs to alleviate CPU load and improve efficiency. However\, existing solutions struggle to handle the growing flow rule space within the NIC\, leading to high miss rates and poor scalability. In this paper\, we introduce Gigaflow\, a novel caching system tailored for deployment on SmartNICs to accelerate vSwitch packet processing. Our core insight is that by harnessing the inherent pipeline-aware locality within programmable vSwitch pipelines—defining policies (e.g.\, L2\, L3\, and ACL) and their execution order (e.g.\, using P4 and OpenFlow)—we can create cache rules for shared segments (sub-traversals) within the pipeline\, rather than caching entire flows. These shared segments can be reused across multiple flows\, resulting in higher cache efficiency and greater rule-space coverage. Our evaluations—performed using Xilinx Alveo U250 data center accelerator running a Gigaflow pipeline written in P4—show that Gigaflow achieves up to a 51% improvement in cache hit rate (average 25% improvement) over traditional caching solutions (i.e.\, Megaflow)\, while capturing up to 450x more rule space within the limited memory of today’s SmartNICs—all while operating at line speed.  \nPublication Link : https://dl.acm.org/doi/10.1145/3676641.3716000 \nSpeaker\nAnnus Zulfiqar is a PhD candidate at the University of Michigan with Professor Muhammad Shahbaz. His research focuses on designing next generation hardware/software abstractions and architectures for emerging data center networking applications. Currently\, he is working on designing a scalable and efficient fast path for the Open vSwitch\, which is a widely used software switch in modern data centers. He is also working on ML for Systems where he has contributed to automatic generation of optimized data plane ML models and the development of scalable decision trees for programmable switches. \n 
URL:https://p4.org/event/p4-developer-days-gigaflow-pipeline-aware-sub-traversal-caching-for-modern-smart-nics/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250529T080000
DTEND;TZID=UTC:20250529T080000
DTSTAMP:20260417T032036
CREATED:20250912T220259Z
LAST-MODIFIED:20250915T225242Z
UID:10000125-1748505600-1748505600@p4.org
SUMMARY:P4 Developer Days - P4 on Silicom ThunderFjord SmartNIC
DESCRIPTION:P4 Developer Days webinar\, “P4 on Silicom ThunderFjord SmartNIC”\nDate: May 29\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nThe integration of P4 into the FPGA of the Silicom ThunderFjord SmartNIC brings unprecedented flexibility and programmability to modern networking. This presentation explores the capabilities of the ThunderFjord SmartNIC\, highlighting how P4 enables dynamic packet processing directly on the hardware. We will delve into the architecture of the SmartNIC\, its role in enhancing network performance\, and the benefits of using P4 to implement custom protocols\, traffic management\, and network offload functions. \nSpeakers \nLars Munch \, Senior Software Engineer\, Silicom Denmark \nLars holds a Master’s degree in Computer Science from the Technical University of Denmark (DTU)\, with research experience in embedded systems. With over two decades of expertise\, he has developed high-performance software solutions for SmartNICs\, IoT devices\, and embedded Linux platforms. Currently\, Lars is a Senior Software Engineer at Silicom Denmark\, where he is responsible for the design\, development\, and optimization of software solutions related to SmartNICs\, playing a key role in delivering advanced networking technologies. \nEleftherios Kyriakakis\, FPGA Developer\, Silicom Denmark \nEleftherios holds a PhD from the Technical University of Denmark (DTU) with a research focus on “Time-predictable End-system Design for Real-Time Communication”.  He specializes in FPGA and ASIC design\, particularly in developing fault-tolerant and real-time systems. His most notable published works include the implementation of a fault-tolerant inter-chip Network-on-Chip (NoC) communication bridge on FPGAs\, memory controllers with single-event upset (SEU) detection\, and research on precise time protocol (PTP) and time-triggered networks. Currently\, Eleftherios is working as an FPGA engineer at Silicom Denmark\, where he is responsible for the design and development of proof-of-concept solutions for SmartNICs. \n 
URL:https://p4.org/event/p4-developer-days-p4-on-silicom-thunderfjord-smartnic/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250506T080000
DTEND;TZID=UTC:20250506T080000
DTSTAMP:20260417T032036
CREATED:20250912T220259Z
LAST-MODIFIED:20250915T225249Z
UID:10000124-1746518400-1746518400@p4.org
SUMMARY:P4 Developer Days - P4 in SDN-based Attack Detection and AI-driven Security Mechanisms
DESCRIPTION:May 6\, 2025 | 8:00am Pacific\nView Video \nView Slides \nAbstract\nSoftware-Defined Networking (SDN) is a promising network architecture that offers greater flexibility and scalability compared to traditional network infrastructures. This flexibility arises from the separation of the data plane from the control plane\, which enables the use of general-purpose devices\, commonly referred to as “dumb devices” in SDN. While this separation enhances network management and administration\, it also imposes processing limitations\, leading to increased overhead on the controller. This is precisely where P4\, a domain-specific programming language for packet processing\, becomes highly beneficial. \nIn the field of network security\, particularly in attack detection\, researchers have proposed various innovative methods. P4 can play a crucial role in advancing these solutions by leveraging a programmable data plane to offload processing tasks from the controller\, thereby achieving a more balanced distribution of computational load between the data and control planes. One of the most critical areas of application in this regard is the detection and mitigation of Distributed Denial-of-Service (DDoS) attacks. \nAdditionally\, there has been a significant rise in AI-based security solutions\, with machine learning (ML) being a prominent subfield. ML enables the development of custom AI agents tailored for specific tasks\, requiring the extraction of relevant features for training purposes. However\, without a programmable data plane\, this approach is impractical in both SDN and traditional networks. With P4\, however\, such implementations become feasible\, opening new possibilities for AI-driven network security solutions. \nIn this webinar\, we will explore the use cases of P4 in SDN-based attack detection and AI-driven security mechanisms\, highlighting its potential to enhance modern network security strategies. \nSpeaker \nReza Fallahi Kapourchali holds an M.Sc. in Computer Networks from Bu-Ali Sina University\, Hamedan\, Iran. His research interests encompass a broad spectrum of critical areas\, including computer network security\, P4 technology\, wireless networks\, 5G networks\, the Industrial Internet of Things (IIoT)\, and network Quality of Service (QoS). His commitment to advancing innovation and knowledge in these fields is evidenced by his published articles\, which contribute to the development of secure and efficient network architectures.
URL:https://p4.org/event/p4-developer-days-p4-in-sdn-based-attack-detection-and-ai-driven-security-mechanisms/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20241028T080000
DTEND;TZID=UTC:20241028T080000
DTSTAMP:20260417T032036
CREATED:20250912T215845Z
LAST-MODIFIED:20250915T225259Z
UID:10000079-1730102400-1730102400@p4.org
SUMMARY:7th European P4 Workshop (EuroP4’24)
DESCRIPTION:Sponsored by AMD \n \n  \nThe 7th edition of EuroP4 was held on October 28th in conjunction with the 32nd IEEE International Conference on Network Protocols (ICNP 2024)\, in Charleroi\, Belgium. \nEuroP4’24 brings together networking researchers and practitioners to discuss cutting-edge\, P4-enabled research and P4-based technology. The workshop provides a venue for presenting and discussing research and projects related to P4\, as well as for more broadly discussing the needs of this research community. The workshop aims to forge new connections between researchers who already work with P4\, introduce more networking researchers to the P4 community\, and seed future top-tier publications\, innovation and contributions to this community. \nKeynotes\nShir Landau Feibish\, Senior Lecturer (Assistant Professor)\nDepartment of Mathematics and Computer Science\, Open University of Israel\nShir is a Senior Lecturer (Assistant Professor) and head of the RUNS lab at The Open University of Israel. Before joining The Open University\, Shir was a postdoctoral researcher at Princeton University. \nShir’s main interests are network telemetry and programmable networks. Her work focuses on building tools for network monitoring by tailoring streaming methods and compact data structures to the computational model and constraints of programmable devices. Shir has received several awards including the Eric and Wendy Schmidt Postdoctoral Award for Women in Mathematical and Computing Sciences and was named one of the Rising Stars in Networking and Communications of 2020 by the N2Women Organization. \n“Time-Aware Network Telemetry in the Data Plane” \nAbstract: Collecting network telemetry is essential for detecting problems in the network. In recent years we have seen an abundance of research on network telemetry in the data plane. Many of these solutions analyze traffic continuously over a long period of time\, while resetting the structure from time to time. If shorter time intervals are needed\, sliding windows are usually used\, yet these incur significant resource and management overhead. However\, often in order to understand what is happening in the network we need to measure events that have recently happened.  \nWe explore the concept of time-aware network telemetry and propose several different paradigms that we utilize for various telemetry tasks. The first is a reactive monitoring scheme for packet loss detection\, that monitors only when needed\, by tailoring the measurement interval to when losses may occur. The second is a mechanism for finding heavy hitter flows of the recent past. Finally\, we explore the option of deleting and decaying a set-membership data structure to allow for more updated information to be maintained.  \n \nMario Baldi\, Fellow\nAMD Research and Advanced Development\nMario Baldi is a Fellow at AMD\, Research and Advanced Development\, and Associate Professor of Information Processing Systems (currently on leave) at Politecnico di Torino (Technical University of Turin)\, Italy. He has held various positions in startup and established companies in the computer networking industry\, as well as several visiting professorships at Universities in four continents\, during over 25 years of professional involvement in the computer networking domain. He authored over 150 scholarly papers on various networking related topics and two books\, and is co-inventor in 35 patents. \n“SmartNICs – P4’s Final Latest Frontier – Challenges and Opportunities Ahead”\nAbstract: While P4 emerged and got established as a language to program packet processing in switches\, it has since been successfully adopted in the context of programmable SmartNICs . This talk first overviews the widely differing architectures of programmable SmartNICs currently available on the market and then discusses the challenges we encounter when deploying P4 for programming them\, as well as the opportunities ahead.\n \nAgenda\n8:00-9:00 – Registration\n  \n9:00-9:10 – Welcome\nSandor Laki – Program Chair\, ELTE Eötvös Loránd University\nSlides\n  \n9:10-10:10 – Industrial Keynote – “SmartNICs – P4’s Final Latest Frontier – Challenges and Opportunities Ahead”\nMario Baldi\, Fellow\, AMD Research and Advanced Development\nSlides\n  \n10:10-10:30 – Coffee break\n  \n10:30-11:00 – “SCION Edge Router for Legacy IP Applications based on Intel Tofino”\nLars-Christian Schulz\, Robin Wehner\, David Hausheer (OVGU Magdeburg\, Germany)\nSlides | Paper\n  \n11:00-11:30 – “P4chaskey: An Efficient MAC Algorithm for PISA Switches”\nMartim Francisco\, Bernardo Ferreira\, Fernando M. V. Ramos (University of Lisbon\, Portugal)\, Eduard Marin (Telefonica Research\, Spain)\, Salvatore Signorello (Telefonica Research\, Spain; University of Lisbon\, Portugal)\nSlides | Paper\n  \n11:30-12:00 – “Deliberately Congesting a Switch for Better Network Functions Performance”\nMariano Scazzariello (KTH Royal Institute of Technology\, Sweden)\, Tommaso Caiazzi (Roma Tre University \,Italy)\, Marco Chiesa (KTH Royal Institute of Technology\, Sweden)\nSlides | Paper\n  \n12:00-14:00 – Lunch break\n  \n14:00-15:00 – Scientific Keynote: “Time-Aware Network Telemetry in the Data Plane”\nShir Landau Feibish\, Assistant Professor\, Open University of Israel \n15:00-15:30 – “Secure In-Band Network Telemetry for the SCION Internet Architecture on Tofino”\nRobin Wehner\, Tony John\, Lars-Christian Schulz\, David Hausheer (OVGU Magdeburg\, Germany)\nSlides | Paper\n  \n15:30-16:00 – Coffee break\n  \n16:00-16:30 – “Towards Real-Time Intrusion Detection in P4-Programmable 5G User Plane Functions”\nAristide Tanyi-Jong Akem (IMDEA Networks Institute\, Spain; Universidad Carlos III de Madrid\, Spain)\, Marco Fiore (IMDEA Networks Institute\, Spain)\nSlides | Paper\n  \n16:30-16:40 – Closing words\n  \nWORKSHOP ORGANISERS \nGeneral Chairs:\n– Fernando Ramos\, University of Lisbon\n– Muhammad Shahbaz\, Purdue University \nProgram Chairs:\n– Amedeo Sapio\, Amazon Web Services (AWS)\n– Sandor Laki\, ELTE Eötvös Loránd University \nPublicity Chair:\n– Csaba Györgyi\, ELTE Eötvös Loránd University / University of Vienna \nProgram Committee:\n– Andreas Kassler (Karlstad University\, Sweden; Technische Hochschule Deggendorf\, Germany)\n– Francesco Paolucci (CNIT\, Italy)\n– Stefan Schmid (TU Berlin\, Germany)\n– Christian E. Rothenberg (University of Campinas\, Brasil)\n– Noa Zilberman (Oxford University\, UK)\n– Gergely Pongrácz (Ericsson\, Hungary)\n– Andy Fingerhut (Cisco Systems\, USA)\n– Nik Sultana (Illinois Institute of Technology\, USA)\n– Sebastiano Miano (Politecnico di Milano\, Italy)\n– Sebastian Gallenmüller (TU Munich\, Germany)\n– Mingyuan Zang (Technical University of Denmark\, Denmark)\n– Masoud Hemmatpour (The Arctic University of Norway\, Norway)\n– Alan Zaoxing Liu (University of Maryland\, USA)
URL:https://p4.org/event/7th-european-p4-workshop-europ424/
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BEGIN:VEVENT
DTSTART;TZID=UTC:20241025T080000
DTEND;TZID=UTC:20241025T080000
DTSTAMP:20260417T032036
CREATED:20250912T220258Z
LAST-MODIFIED:20250915T225333Z
UID:10000123-1729843200-1729843200@p4.org
SUMMARY:Japan P4 Users Group
DESCRIPTION:The 2024 Japan P4 Users Group was hosted as a hybrid in-person and online event and included P4-related presentations and exhibits. View the agenda and resources. Talks were presented in Japanese and video can be accessed here.
URL:https://p4.org/event/japan-p4-users-group/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20241003T080000
DTEND;TZID=UTC:20241003T080000
DTSTAMP:20260417T032036
CREATED:20250912T220242Z
LAST-MODIFIED:20251001T192054Z
UID:10000122-1727942400-1727942400@p4.org
SUMMARY:2024 P4 Workshop
DESCRIPTION:The 2024 P4 Workshop took place October 3rd\, and was hosted and sponsored by Google. This in-person event took place at Google’s Moffett Park Campus in Sunnyvale\, California and offered an opportunity for the P4 ecosystem to share knowledge and experiences with the broader community and to facilitate collaboration. \nView individual videos and slides on-demand from the event below! Or\, view YouTube Playlist. \nInvited Talks\n\n\n  \n\n\n\n\n \nTitle\nVideo\nSlides\n\n\n\n\n\nWelcome\, State of P4 & 2024 Distinguished Contributor Award \nAndy Fingerhut\, Principal Engineer\, Intel\n\n\n\n\n\n\nKeynote – Navigating Internet Research with P4: Solutions for Performance and Security\nMaria Apostolaki\, Assistant Professor of Electrical and Computer Engineering\, Princeton University\n\n\n\n\n\n\nFireside Chat with Martin Casado\nMartin Casado\, General Partner\, Andreessen Horowitz\nNate Foster\, Professor Computer Science\, Cornell University\n\n\n\n\n\n\nP4 on Hardware: The Future\nKonstantin Weitz\, Staff Software Engineer\, Google (Moderator)\nVipin Jain\, Sr Fellow Engineer\, AMD\nAnjali Singhai Jain\, Network Architect\, Intel\n\n\n\n\n\nIn-Depth Talks\n\n\n  \n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n\n\n\n\nPast\, Present and Future of P4\nDeb Chatterjee\, Sr Director Software Engineering\, Intel\n\n\n\n\n\n\nCompiler-assisted Kernel-based P4 Pipeline Offloading Using Intel IPU\nDeb Chatterjee\, Sr Director Software Engineering\, Intel\nNeha Singh\, Staff Software Engineer\, Intel\n\n\n\n\n\n\nTowards the Performant P4C\nAnton Korobeynikov\, Principal Software Engineer\, Compiler Development\, Access Softek Toolchains\n\n\n\n\n\n\nSupporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme\nBill Pontikakis\, Sr Research Associate\, Polytechnique Montréal\nFrançois-Raymond Boyer\, Professeur\, Polytechnique Montréal \n\n\n\n\n\n\n\nSONiC DASH on Intel IPU2100\nShweta Shrivastava\, Cloud Software Engineer\, Intel\nNamrata Limaye\, Director Software Engineering\, Intel \n\n\n\n\n\n\nInternals of the Intel Tofino Compiler\nGlen Gibb\, Compiler Engineer\, Intel\n\n\n\n\n\n\nP4-SpecTec – Mechanized Language Definition for P4\nJaehyun Lee\, Student\, KAIST\n\n\n\n\n\n\nCentralized Telemetry and Security Enforcement Using SONiC and P4\nShekher Bulusu\, Sr Manager Software Engineering\, GEICO\nPawan Ravi\, Sr Staff Engineer\, GEICO\nJames Choi\, Sr Engineering Manager\, GEICO\n\n\n\n\n\n\nModeling Hardware Blocks of Network ASICs using P4\nJean Tourrilhes\, Researcher\, HPE\n\n\n\n\n\n\nIn-Memory Key-Value Store Live Migration with NetMigrate\nZeying Zhu\, PhD Student\, University of Maryland\n\n\n\n\n\n\nP4-Based Automated Reasoning (P4-BAR) for the (Networking) Masses!\nSteffen Smolka\, Staff Software Engineer\, Google\nJonathan DiLorenzo\, Software Engineer\, Google\n\n\n\n\n\n\nScaling P4-Based Automated Reasoning (Performance and Coverage)\nAli Kheradmand\, Senior Software Engineer\, Google\nMeghana Sistla\, PhD Student\, University of Texas at Austin\n\n\n\n\n\n\nP4HIR: Toward Bridging P4C with MLIR\nBili Dong\, Software Engineer\, Google\n\n\n\n\n\nDemos\n\n  \n\n\n\n\n \nTitle\n \nAbstract\n\n\n \n\n\n\nSONiC DASH on Intel IPU2100\nNamrata Limaye\, Director Software Engineering\, Intel \n\n\n \n\n\n\nData Center Routing GEICO SDN Controller and GEICO SONiC Using P4\nSunil Kumar Rawookar\, Staff Engineer\, GEICO Tech\n\n\n \n\n\n\nOffload NAT and Routing onto Intel IPU Using P4-TC\nNeha Singh\, Staff Software Engineer\, Intel\n\n\n \n\n\n\nP4 IDE: An Integrated Development Environment for P4-based Data Plane Development\nNamrata Limaye\, Director Software Engineer\, Intel\n\n\n \n\n\nP4Docker: Simplifying P4 Switch Testbeds with Docker Integration \nLucas Trombeta\, PhD Candidate\, Federal University of ABC (UFABC)\n\n\n \n\n\n\nSupporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme\nBill Pontikakis\, Sr Research Associate\, Polytechnique Montréal\nFrançois-Raymond Boyer\, Professeur\, Polytechnique Montréal \n\n\n\n\nPoster\n\n  \n\n\n\n\n \nTitle\nAbstract\n\n\n\n\n\n\nBabel: The Tower So Far\nVictor Rios\, Software Engineer\, Google\n\n\n\n\nGeneral Chair – Nate Foster \nProgram Co-Chairs – Andy Fingerhut\, Muhammad Shahbaz \nProgram Committee\n– Jehandad Khan\, AMD\n– Ori Rottenstreich\, Technion\n– Vishal Shrivastav\, Purdue University\n– Gianni Antichi\, Politecnico di Milano and Queen Mary University of London\n– Ben Pfaff\, Feldera\n– Ajay Lotan Thakur\, Intel Corp\n– Victor Liu\, University of Michigan\n– Vladimir Gurevich\, P4ica\n– Tushar Swamy\, unaffiliated\n– Yiming Qiu\, University of Michigan\n– Amedeo Sapio\, Amazon Web Services\n– Lavanya Jose\, Google
URL:https://p4.org/event/2024-p4-workshop-postevent/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=UTC:20240905T090000
DTEND;TZID=UTC:20240905T090000
DTSTAMP:20260417T032036
CREATED:20250912T215847Z
LAST-MODIFIED:20250915T225417Z
UID:10000081-1725526800-1725526800@p4.org
SUMMARY:2024 P4 GSoC Projects - Webinar
DESCRIPTION:Thursday\, September 5\, 2024\n9:00am Pacific \nView Video \nLearn about the four exciting projects hosted by the P4 Language Organization as part of Google‘s Summer of Code (GSoC) 2024. Each of the project contributors present their projects followed by a short discussion. \nP4 Projects in GSoC\n\nView Project Details\nImproving the documentation of the P4 Compiler\nContributor: Adarsh Rawat\, Graphic Era Deemed to be University\nMentors: Fabian Ruffy\, Davide Scano \nBuilding a Formatter for the P4 Language\nContributor: Nitish Kumar\, Indian Institute of Technology Kharagpur\nMentors: Bili Dong\, Fabian Ruffy \nIntroducing PNA support to BMv2\nContributor: Rupesh Chiluka\, University of Hyderabad (UoH)\nMentors: Hari Thantry\, Debobroto Das Robin \nP4-Enabled Container Migration in Kubernetes\nContributor – Stanislav Korosin\, Technische Universität Berlin\nMentors: Davide Scano\, Radostin Stoyanov
URL:https://p4.org/event/2024-p4-gsoc-projects-webinar/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20240821T080000
DTEND;TZID=UTC:20240821T080000
DTSTAMP:20260417T032036
CREATED:20250912T215846Z
LAST-MODIFIED:20250915T225425Z
UID:10000080-1724227200-1724227200@p4.org
SUMMARY:P4 Developer Days - NSF Cybertraining Project
DESCRIPTION:August 21\, 2024 | 8:00am Pacific\nView Recording\nA key barrier to the faster adoption of programmable data planes (e.g.\, P4 switches\, SmartNICs\, end-hosts) is the lack of engaging training materials. This NSF Cybertraining project aims to address this challenge by developing hands-on virtual labs (vLabs) for online instruction. These vLabs will be deployed on FABRIC\, an NSF-funded international infrastructure for research at scale\, and on the Academic Cloud\, a training and research cloud system maintained by the University of South Carolina. The team has already created approximately 30 vLabs on BMv2\, the P4 software switch. The project will now focus on open-source technologies related to SmartNICs and end-host stacks (e.g.\, PNA\, P4-DPDK\, P4TC\, P4-eBPF\, etc.). The developed vLabs will be open-source and available to the community. Learners will be provided with detailed laboratory manuals and access to the training platforms\, which are accessible from the Internet using a regular web browser (no SSH or installations required). \nPresenters \nElie Kfoury\, University of South Carolina\nJorge Crichigno\, University of South Carolina
URL:https://p4.org/event/p4-developer-days-nsf-cybertraining-project/
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BEGIN:VEVENT
DTSTART;TZID=UTC:20240429T080000
DTEND;TZID=UTC:20240501T080000
DTSTAMP:20260417T032036
CREATED:20250912T220241Z
LAST-MODIFIED:20250915T225437Z
UID:10000120-1714377600-1714550400@p4.org
SUMMARY:ONE Summit 2024: P4-Based Automated Reasoning
DESCRIPTION:  \nCheck out the video and slides by P4 TST member Steffen Smolka\, “P4-based Automated Reasoning” which was featured at The Linux Foundation’s One Summit 2024. In his talk he discusses how P4 is now being used as a specification language for network programmable and non-programmable pipelines. He discusses how Google and others have been leveraging such machine-readable\, unambiguous\, vendor-agnostic specifications of their switches to increase network reliability and development as well as allow the SDN controller to interoperate seamlessly with switches form different vendors. \n  \nView Video \nReview Slides
URL:https://p4.org/event/one-summit-2024-p4-based-automated-reasoning/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20240402T080000
DTEND;TZID=UTC:20240402T080000
DTSTAMP:20260417T032036
CREATED:20250912T220231Z
LAST-MODIFIED:20250915T225500Z
UID:10000119-1712044800-1712044800@p4.org
SUMMARY:P4 Open Source Developer Days: P4 Traffic Generator and Analyzer
DESCRIPTION:April 2nd 2024 \nIn case you missed it\, you can now watch the recording of the recent P4 Developer Days Talk by Steffen Lindner (University of Tuebingen) on the P4TG traffic generator and analyzer. \n“We present P4TG\, an open-source P4-based traffic generator (TG) which runs on the programmable Intel Tofino ASIC. In generation mode\, P4TG is capable of generating traffic up to 1 Tb/s split across 10x 100 Gb/s ports. Thereby it measures rates directly in the data plane. Generated traffic may be fed back from the output to the input ports\, possibly through other equipment\, to record packet loss\, packet reordering\, inter-arrival times (IATs) and sampled round trip times (RTTs). Further\, it supports VLAN\, QinQ\, and MPLS encapsulation. In analysis mode\, P4TG measures rates on the input ports and IATs\, and forwards traffic through its output ports. Existing software or P4-based traffic generators either lack the required accuracy\, do not support high data rates\, or do not provide sufficiently integrated measurement capabilities.”
URL:https://p4.org/event/p4-open-source-developer-days-p4-traffic-generator-and-analyzer/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20231208T080000
DTEND;TZID=UTC:20231208T080000
DTSTAMP:20260417T032036
CREATED:20250912T220230Z
LAST-MODIFIED:20250915T225515Z
UID:10000118-1702022400-1702022400@p4.org
SUMMARY:Euro P4 2023
DESCRIPTION:EuroP4 2023 took place December 8th in conjunction with ACM CoNEXT 2023 in Paris (France). This event brought together networking researchers and practitioners to discuss cutting-edge\, P4-enabled research and P4-based technology. The workshop provided a venue for presenting and discussing research and projects related to P4\, as well as for more broadly discussing the needs of this research community. The workshop aimed to forge new connections between researchers who already work with P4\, introduce more networking researchers to the P4 community\, and seed future top-tier publications\, innovation and contributions to this community.\nView proceedings from the 2023 EuroP4 Workshop \n  \nSession 1: P4 Networking\n\nLANTERN: Layered Adaptive Network Telemetry Collection for Programmable Data Planes\nKaiyu Hou (Alibaba Cloud)\, Dhiraj Saharia (Georgetown University)\, Vinod Yegneswaran (SRI International)\, Phil Porras (SRI International) \n\nAbstract: \nManaging next-generation enterprise networks requires collecting and analyzing enormous volumes (tens of Tbps) of network traffic data in real time to detect potential anomalies\, classify attacks\, identify root causes\, and rapidly deploy effective mitigations. Conducting robust and scalable analysis on such traffic volumes is a daunting ”haystack” problem that demands intelligent strategies to winnow traffic to extract and pinpoint ”needles” of interest. Recent advances in software-defined networking and programmable dataplanes\, that enable dynamic reconfiguration of switching hardware to adapt to changing traffic conditions\, provide a foundational building block. However\, they lack the resources and programming primitives for complex computational models. \nToward that end\, we present LANTERN\, a layered and adaptive network telemetry system that facilitates joint collection and analysis of network traffic at multiple resolutions in coordination with the controller. Our design offloads complex machine-learning analysis to the controller\, while still enabling proactive telemetry refinement and reactive mitigation triggers at the data-plane level. We evaluate our layered approach by replaying a labeled CIC-IDS attack dataset through both software and hardware P4 switches. LANTERN is able to detect most anomalies\, accurately classify them\, and introduces negligible switching overhead (1% latency). \nRead Paper | View Slides \n  \nPer Priority Data Rate Measurement in Data Plane \nHabib Mostafaei (Eindhoven University of Technology)\, Georgios Smaragdakis (Delft University of Technology) \nAbstract: \nMany applications\, such as video streaming\, congestion control\, and server selection\, can benefit when the data rate of different priority groups between two endpoints is accurately estimated over the end-to-end path. With the introduction of programmable networks\, e.g.\, P4\, it is now possible to offload the measurements to the data plane of intermediate devices. Recently\, tools have been developed to react to changes in available bandwidth\, but a tool to accurately estimate end-to-end per-priority data rates needs to be added. This motivates us to design and implement a new end-to-end and per-priority data rate estimation tool\, PrioMeter. PrioMeter can accurately report the data rate per priority group of flows in programmable networks using high-precision timestamps for arbitrary traffic scales. PrioMeter leverages two primitives: quantization and truncation\, to achieve its goals. We implement PrioMeter in P4 and test it on BMv2 switches\, and our preliminary results using NS3 simulations show that it can accurately estimate the data rate of different priority flows with minimal overhead. \nRead Paper | View Slides \n  \nCryptographic Path Validation for SCION in P4 \nLars-Christian Schulz (OVGU Magdeburg)\, Robin Wehner (OVGU Magdeburg)\, David Hausheer (OVGU Magdeburg) \nAbstract: \nSCION has been proposed as a new Internet architecture addressing security and scalability shortcomings in the current Internet. Multiple real-world deployments of SCION exist already\, nevertheless few hardware implementations of SCION routers are available. \nIn this paper\, we implement a SCION border router on a programmable 12.8 Tbit/s Intel Tofino 2 switch. Our router utilizes the multiple separately programmable packet pipelines of Tofino 2 in order to compute SCION’s AES-CMAC-based hop authenticators in general-purpose P4 without assistance from specialized hardware. \nUsing three out of four available pipelines\, we achieve 394.7 Gbit/s throughput per port on 8 ports for a total of 3.16 Tbit/s capacity. Using only two pipelines we still achieve line rate throughput on 4 ports for a total of 1.58 Tbit/s capacity. To our knowledge there is no other SCION router including the AES-CMAC validation that offers a comparable performance. \nRead Paper | View Slides \n\n  \n\n\nSession 2 – P4 Control & Targets\n\n\nIntroducing P4TC – A P4 Implementation on Linux Kernel using Traffic Control\nJamal Hadi Salim (Mojatatu Networks)\, Deb Chatterjee (Intel Corporation)\, Victor Nogueira (Mojatatu Networks)\, Pedro Tammela (Mojatatu Networks)\, Tomasz Osinski (Intel Corporation)\, Evangelos Haleplidis (Mojatatu Networks)\, Balachandher Sambasivam (Intel Corporation)\, Usha Gupta (Intel Corporation)\, Komal Jain (Intel Corporation)\, Sosutha Sethuramapandian (Intel Corporation) \nAbstract: \nThe networking industry is at an inflection point with ever increasing network link capacities coupled with the presence of programmable hardware ASICs. These set of circumstances call out for a robust approach to hardware and software co-existence for network programmability. \nP4TC is a P4 Linux kernel-native implementation on top of the Linux Traffic Control (TC) infrastructure that provides a vendor-neutral\, kernel-independent and architecture-independent interface for Match-Action packet processing compatible with the P4 specification. P4TC facilitates both a hardware datapath and a functionally equivalent kernel eBPF-assisted software datapath making it ideal to deal with both high speed links and programmable hardware. \nIn this paper\, we describe the goals and motivation of P4TC\, the design and architecture as well as illustrate the different concepts of the P4TC infrastructure via an example of a simple L2 switch. \nRead Paper | View Slides \n  \n\nNAP: Programming data planes with Approximate Data Structures\nMengying Pan (Princeton University)\, Hyojoon Kim (University of Virginia)\, Jennifer Rexford (Princeton University)\, David Walker (Princeton University) \nAbstract: \nMany applications that run on programmable data planes rely on approximate data structures\, due to insufficient in-network memory. However\, programming with approximate data structures is challenging because it requires (1) expertise in streaming algorithms to select the data structures that best match an application’s requirements\, (2) meticulous configuration to minimize approximation error while fitting within the hardware constraints\, and (3) proficiency in the low-level P4 language. To address these issues\, we propose NAP\, a high-level network programming language. The core of NAP is the versatile approximate dictionary abstraction that captures a wide range of compact data structures\, while allowing programmers to simply specify the kinds of error an application can tolerate. We demonstrate the language’s expressiveness\, conciseness\, and efficiency through a variety of network applications\, each compiling to P4 for the Intel Tofino in less than a second and featuring 25X–50X fewer lines of code compared to the P4 output. We evaluate an approximate stateful firewall written in NAP with real campus traffic\, achieving performance consistent with the predicted accuracy. \nRead Paper | View Slides \n  \nP4EAD: Securing the In-band Control Channels on Commodity Programmable Switches \nArchit Bhatnagar (Birla Institute of Technology & Science\, Pilani)\, Xin Zhe Khooi (National University of Singapore)\, Cha Hwan Song (National University of Singapore)\, Mun Choon Chan (National University of Singapore) \nAbstract: \nConventionally\, the control channel on network switches has always been out-of-band. With the emergence of high-performance systems built upon programmable switches\, the out-of-band control channel has become the bottleneck. Thus\, there is an emerging trend of implementing the control channel in the data path (i.e.\, in-band) on programmable switches to achieve high throughput and low-latency control actions. However\, the use of in-band control channels comes with the risk of security vulnerabilities that have not been explored in prior literature. In this paper\, we present P4EAD\, a cryptographic primitive to secure the in-band control channels on programmable switches entirely in the data plane. This ensures the integrity\, authenticity\, and confidentiality of in-band control messages. We conduct micro-benchmarks on P4EAD and demonstrate its integration with an existing high-performance in-band control framework\, showcasing minimal performance impact when securing the control channel. \nRead Paper | View Slides \n\n  \n\n\nPosters and Demos Session\nPoster: High-Speed Per-Packet Checksums on the Intel Tofino\nDavid Grölle (OVGU Magdeburg)\, Lars-Christian Schulz (OVGU Magdeburg)\, Robin Wehner (OVGU Magdeburg)\, David Hausheer (OVGU Magdeburg) \nAbstract: \nPath-aware networking has introduced new possibilities to monitor and control network access and solved a multitude of modern-day Internet security issues. Being able to authorize usage of specific paths enables network operators to offer high-quality services to customers requiring highly reliable network access. \nCurrently\, securing a network path or an end host is only possible by using high-level solutions like VPNs. With EPIC-HP (Every Packet Is Checked – Hidden Path)\, it has been shown that it is possible to move this functionality down into the network itself. EPIC-HP extends the path-aware Internet architecture SCION by offering per-packet checksums\, adding authentication to network traffic. This is used to combat DoS attacks on the network’s end hosts and give high-priority access to specific end users. In this paper\, we show that it is possible to implement the functionality of EPIC-HP along with SCION on the Intel Tofino 2 ASIC. EPIC-HP requires AES-based MAC verification with per-path keys in the data plane. By using the multi-pipeline structure of the Tofino\, we implemented the required AES and AES-CMAC cryptography using three pipes of the switch’s total four independent pipes. \nThe throughput we achieve is an order of magnitude above the data rates previously achieved for EPIC-HP and is a significant step towards a more secure Internet. \nRead Paper \n  \nPoster: P4DME: DNS Threat Mitigation with P4 In-Network Machine Learning Offload \nJuan Vanerio (University of Vienna)\, Csaba Györgyi (University of Vienna)\, Stefan Schmid (TU Berlin\, Fraunhofer SIT) \nAbstract: \nThe ever-evolving cybersecurity landscape demands innovative solutions to safeguard critical network infrastructure such as the Domain Name System (DNS). This paper presents P4DME\, a novel approach that harnesses the potential of Machine Learning (ML) in conjunction with P4 programmable switches to tackle DNS threats efficiently. P4DME’s primary benefit lies in offloading filtering from resource-intensive ML processing tasks on dedicated servers. This offloading boosts the overall traffic throughput that can be inspected or achieves the same throughput with reduced resource consumption while preserving the servers’ capabilities for high-performance threat identification. This work uses P4-based in-network elements to handle crucial DNS threats\, dynamic white- and blacklisting\, and an online popularity-based anomaly detection heuristic. The latter serves as a trigger for dedicated ML-based inspection. Furthermore\, we introduce in-network mitigation filters updated through the control plane to provide adaptable and responsive threat mitigation. Preliminary simulation results show more than 99.9% offload ratio at 5% increased False Negative Ratio. \nRead Paper \n  \nPoster: Maintaining Sets With Deletions in the Data Plane \nJonathan Diamant (The Open University of Israel)\, Shir Landau Feibish (The Open University of Israel) \nAbstract: \nSets are one of the most fundamental data types in Computer Science\, and data structures used to maintain sets are used in many algorithms. These structures normally support three basic operations: insertion\, look-up (i.e. set-membership query)\, and deletion. The most common set-membership data structure used in the data plane is the Bloom Filter (BF). While BFs are relatively easy to adapt to the data plane\, they offer a limited set-membership functionality as they do not support deletions. If deletions are required\, a Counting Bloom Filter (CBF) (which maintains counters instead of bits) may be used. Yet\, if a key was inserted multiple times\, multiple deletions would be needed to completely remove the key from the structure. We present MEM-D\, a fast and lightweight set-membership data structure for the data plane\, which supports all three operations: look-up\, insertion\, and deletion. MEM-D supports the uniqueness property\, meaning that a key would be removed with a single deletion operation even if it was inserted multiple times. MEM-D provides a false positive (FP) error rate similar to the rate of the standard BF and additionally may incur a small false negative (FN) error. We have implemented MEM-D on a hardware Tofino target using P4. To the best of our knowledge\, MEM-D is the first data structure for set-membership in the data plane\, which supports deletion. \nRead Paper \n  \n\nPoster: Adaptive In-Network Inference using Early-Exits\nHeewon Kim (Korea University)\, Seongyeon Yoon (Korea University)\, Sangheon Pack (Korea University) \nAbstract: \nIn-network (or on-path) inference over programmable data planes allows fast and low-overhead inference in deep neural networks. In this work\, we propose an adaptive approach to strike the balance between accuracy and processing cost. To be specific\, the confidence score is evaluated at the end of each layer\, and an early exit is triggered if the confidence score is sufficiently high. We implement this early-exit scheme over BMv2 software switches and the results demonstrate that the proposed scheme successfully controls the trade-off by making use of the confidence score. \nRead Paper \n  \nDemo: Enabling DNN-Based Inference in the Network Data Plane \nSiddhartha (AMD)\, Justin Tan (AMD & NUS)\, Rajesh Bansal (AMD)\, Chee Chung Chan (AMD)\, Yuta Tokusashi (AMD)\, Yew Kwan Chong (AMD)\, Haris Javaid (AMD)\, Mario Baldi (AMD) \nAbstract: \nAdvancements in programmable packet processing technologies have fostered innovation across a range of networking applications. Integration of deep neural networks (DNN) in the network data plane\, however\, has remained largely unaddressed due to the high compute requirements of the underlying algebraic kernels. In this paper\, we show how P4 packet processing pipelines can be augmented with DNN inference engines on devices readily available in the market today. We share a network security case study\, where we train a DNN-based anomaly detector that classifies active traffic flows as either malicious or benign using per-packet inference. Our implementation runs on an AMD AlveotextsuperscriptTM U250 FPGA accelerator card\, and is capable of servicing network traffic of up to approx~98~Mpps on 100~GbpE links. \nRead Paper \n  \nWorkshop General Chairs\nFernando Ramos\, University of Lisbon\nMuhammad Shahbaz\, Purdue University \nProgram Chairs\nVladimir Gurevich\, P4ica\nSalvatore Signorello\, Telefonica Research\, Spain \nPublicity Chairs\nDenise Barton\, ONF\nSandor Laki\, Eötvös Loránd University \nProgram Committee\nAlan Lo\,  NVIDIA\nAlan Zaoxing Liu\, University of Maryland\nAndy Fingerhut\, Intel\nAnirudh Sivaraman\, New York University\nChristian Esteve Rothenberg\, University of Campinas\nDaehyeok Kim\, University of Texas at Austin\nDavide Sanvito\, NEC Labs\nEnnan Zhai\, Alibaba Cloud\nGianni Antichi\, Politecnico di Milano & Queen Mary University of London\nJiarong Xing\, Rice University\nMario Baldi\, AMD & Politecnico di Torino\nNate Foster\, Cornell University\nNik Sultana\, Illinois Institute of Technology\nRobert Soulé\, Yale University\nShir Landau Feibish – The Open University of Israel \n 
URL:https://p4.org/event/euro-p4-2023/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20230424T080000
DTEND;TZID=UTC:20230425T080000
DTSTAMP:20260417T032036
CREATED:20250912T220028Z
LAST-MODIFIED:20250915T225525Z
UID:10000100-1682323200-1682409600@p4.org
SUMMARY:2023 P4 Workshop
DESCRIPTION:The P4 Workshop is an opportunity for the P4 ecosystem to share knowledge and experiences with the broader community and to facilitate collaboration. The workshop incorporates insights and perspectives from the P4 community across the following key areas: \n\nP4 language\nP4 targets\nP4 tool chain\nP4 use cases & applications\nControl plane or network OS for P4 targets\nExtensions to P4\nCross-cutting work between P4 and related systems such as eBPF and service meshes.\n\nView individual videos and slides below! Or\, view YouTube playlist. \nKeynotes\n\n\n\n\n\n \nTitle\nVideo\nSlides\n\n\n\n\n\n\nWelcome & State of P4\nMina Tahmasbi Arashloo\, Program Chair\, University of Waterloo\nAndy Fingerhut\, Principal Engineer\, Intel\n\n\n\n\n\n\nFireside Chat with Nick McKeown\nNick McKeown\, P4 Co-founder & Evangelist\nLarry Peterson\, Chief Scientist\, ONF\n\n\n\n\n\n\nDeveloping Real World Applications Using P4-Based Architecture\nKrishna Doddapaneni\, Corporate Vice President\, AMD Pensando\n\n\n\n\n\n\nP4 HAL for Network Virtualization\nParveen Patel\, Google Cloud\, Senior Director Engineering\, Google Cloud\n\n\n\n\n\n\nThe Power of Fully-Specified Data Planes\nRob Sherwood\, Chief Technology Officer\, NEX Cloud Networking Group\, Intel\n\n\n\n\n\n\nFrom Programmability to Fungibility\nAng Chen\, Assistant Professor Computer Science\, Rice University\n\n\n\n\n\n\nCan SmartNICs Help Accelerate Distributed Systems?\nArvind Krishnamurthy\, Short-Dooley Professor\, Paul G. Allen School of Computer Science & Engineering\, University of Washington\n\n\n\n\n\nIn-Depth Talks\n\n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n\n\n\n\nEscaping Babel: The Flow Must Go On\nVictor Rios\, Google\n\n\n\n\n\n\nOpenConfig Co-Existence with P4 Using TDI\nJames Choi\, Cloud SW Architect\, Intel\n\n\n\n\n\n\nFormalizing and Extending P4’s Type System\nParisa Ataei\, Postdoc\, Cornell University\n\n\n\n\n\n\nEffective DGA Family Classification Using a Hybrid Shallow and Deep Packet Inspection Technique on P4 Programmable Switches\nAli AlSabeh\, University of South Carolina\n\n\n\n\n\n\nSegment Routing Proxy Device implemented Using P4 on FPGA with Zero CPU Overhead\nMiroslaw Walukiewicz\, Intel\n\n\n\n\n\n\nHardware Offload Driver with P4-TC\nAnjali Singhai Jain\, Network Architect\, Intel\nNamrata Limaye\, Intel\n\n\n\n\n\n\nP4TC: Linux Kernel P4 implementation Approaches and Evaluation\nDeb Chatterjee\, Intel\nJamal Hadi Salim\, Mojatatu Networks\n\n\n\n\n\n\nAugmenting P4-DPDK Software Pipelines with Accelerators: the IPsec Use Case\nAndy Fingerhut\, Intel\n\n\n\n\n\nLightning Talks\n\n  \n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n \n\n\n\nIntent-based Platform Leverages Programmable Networking for Optimizing Edge\nDave Duggal\, Founder/CEO\, EnterpriseWeb\nWilliam Malyk\, Chief System Architect\, EnterpriseWeb\n\n\n\n \n\n\n\nA Language Engineering Approach to Support the P4 Coding Ecosystem\nAlexandre Lachance\, Graduate Student\, McMaster University\n\n\n\n \n\n\n\nEnhancing Blockage Detection and Handover on 60 GHz Networks with P4 Programmable Data Planes\nAli AlSabeh\, Computer Science PhD Student\, University of South Carolina\n\n\n\n \n\n\n\nP4MS: Leveraging Passive Measurements from P4 Switches to Dynamically Modify a Router’s Buffer Size\nJose Gomez\, Graduate Assistant\, University of South Carolina\n\n\n\n\n\nP4 Working Group Update\n\n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n \n\n\n\nWhat’s New in P4-16\nMihai Budiu\, P4 Language Design Working Group Co-Chair\n\n\n\n \n\n\n\nP4.org Architecture Work Group\nMario Baldi\, P4 Architecture Working Group Co-Chair\nAndy Fingerhut\, P4 Architecture Working Group Co-Chair\n\n\n\n \n\n\n\nP4 API Working Group Annual Wrap-up\nChris Sommers\, API Working Group Co-Chair\nSteffen Smolka\, API Working Group Co-Chair\n\n\n\n\n\nDemos\n\n  \n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n \n\n\n\nA Language Engineering Approach to Support the P4 Coding Ecosystem\nAlexandre Lachance\, Graduate Student\, McMaster University\n\n\n\n \n\n\n\nDemo to Offload Networking Pipeline on Intel IPU E2000 Using P4 Control Plane\nNupur Uttarwar\, Cloud Software Engineer\, Intel\nNamrata Limaye\, Senior Engineering Manager\, Cloud Software\, Intel\n\n\n\n \n\n\n\nEnabling P4 hands-on Training Using Hardware Switches in a Cloud System at the University of South Carolina\nJose Gomez\, Graduate Assistant\, University of South Carolina\n\n\n\n \n\n\n\nEnhancing Blockage Detection andHandover on 60 GHz Networks with P4 Programmable Data Planes\nAli AlSabeh\, Research Assistant\, University of South Carolina\n\n\n\n\n\nPosters\n\n  \n\n\n\n\n \nTitle\nDetails\n\n\n\n\n\n\nA Testbench for Testing Programmable Traffic Managers in a Software Environment\nBill Pontikakis\, Research Associate\, Polytechnique Montreal\n\n\n\n\n\nCasual Network Telemetry\nYunhe Liu\, Research Assistant\, Cornell University\n\n\n\n\n\nEnhancing Blockage Detection and Handover on 60 GHz Networks with P4 Programmable Data Planes\nAli AlSabeh\, Research Assistant\, University of South Carolina\n\n\n\n\n\nExtending the P4 Language to Facilitate the Use of Stateful Constructs\nJorg Ehmer\, Polytechnique Montreal\n\n\n\n\n\nIntent-based Platform Leverages Programmable Networking for Optimizing Edge\nDave Duggal\, Founder/CEO\, EnterpriseWeb\nWilliam Malyk\, Chief System Architect\, EnterpriseWeb
URL:https://p4.org/event/2023-p4-workshop/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20230414T111500
DTEND;TZID=UTC:20230414T111500
DTSTAMP:20260417T032036
CREATED:20250912T220230Z
LAST-MODIFIED:20250915T225541Z
UID:10000117-1681470900-1681470900@p4.org
SUMMARY:FOSSASIA Summit 2023
DESCRIPTION:April 14th | 11:15 am SGT \nAris Cahyadi Risdianto\, ONF Ambassador and Research Fellow\, National University of Singapore\, presented “Develop and Verify Networking Program with P4 and Mininet\,” at FOSSASIA Summit 2023. \nAbstract: P4 (programming protocol-independent packet processors) is a special language to define how the network packet forwarding process is built independently from the underlying hardware. It can be used to dynamically reconfigure the forwarding process on the different target hardware\, such as ASIC\, FPGA\, or SmartNIC. Users can write complete networking programs that includes in-band telemetry/measurement\, traffic load-balancing\, anti-DDoS\, packet broker\, and offload protocols. The program can be tested using widely available network emulator\, called Mininet\, so that the behavior of packet forwarding can be verified before it is deployed in the real target hardware. In this presentation\, we will quickly go through on how the P4 program looks like\, how to compile\, and how it is verified using Mininet emulator software.
URL:https://p4.org/event/fossasia-summit-2023/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20230220T143000
DTEND;TZID=UTC:20230302T160000
DTSTAMP:20260417T032036
CREATED:20250912T220224Z
LAST-MODIFIED:20250915T225616Z
UID:10000114-1676903400-1677772800@p4.org
SUMMARY:2023 APRICOT APNIC 55
DESCRIPTION:March 1st | 2:30 – 4:00 pm | Visayas Ballroom \nView Video (1:29) \nCheck out this insightful tutorial\, “P4 Programming Protocol-Independent Packet Processor”\, now on-demand\, by ONF Ambassador and National University of Singapore (NAS) Research Fellow\, Aris Cahyadi Risdianto. In his talk he provides an introduction to P4 and data plane programmability using the P4 programming language\, concluding with a demo on programming a switch using P4.
URL:https://p4.org/event/2023-apricot-apnic-55/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20221209T080000
DTEND;TZID=UTC:20221209T080000
DTSTAMP:20260417T032036
CREATED:20250912T220205Z
LAST-MODIFIED:20250915T225647Z
UID:10000108-1670572800-1670572800@p4.org
SUMMARY:Euro P4 2022
DESCRIPTION:EuroP4 2022 took place December 9th and was held in conjunction with CoNEXT 2022 (December 6-9\, 2022) in Rome\, Italy. \nThe 5th European P4 Workshop (EuroP4) brought together networking researchers to discuss cutting-edge P4-based research and projects\, P4-based tools\, and the needs of the community. The workshop created an opportunity to forge connections between researchers\, introduce more networking researchers to the P4 community\, and seed future top-tier publications and innovation. \nView proceedings from the Euro P4 Workshop. \nSESSION: Security\nBACKORDERS: Using Random Forests to Detect DDoS Attacks in Programmable Data Planes \nBruno Coelho (Federal University of Rio Grande do Sul (UFRGS))\, Alberto Schaeffer-Filho (Federal University of Rio Grande do Sul (UFRGS)\nNetworks and the services they support form the communication backbone of our society\, and it is important that potential Distributed Denial of Service (DDoS) attacks are detected quickly\, in order to avoid or minimize the impact they may have on the availability of services. Recent technological advances in programmable networks – specifically the programmability of data planes in switches and routers\, have made available new ways of detecting such attacks. By relying on this newfound possibility\, this paper proposes the utilization of a Random Forest (RF) to aid in quickly and accurately detecting DDoS attacks in a programmable switch. Random forests utilize several classification trees\, each of them for independently classifying an input as one of a set of classes. Here\, each decision tree will classify a network flow as potentially malicious\, i.e. part of a DDoS attack\, or a legitimate user flow. Despite utilizing multiple classification trees to improve accuracy\, random forests are relatively lightweight\, with each tree requiring few and simple computations to arrive at a classification. Our results show that even small RFs\, requiring as few as 63 match+action table entries\, can achieve F1-Scores of over 90%. \nRead Paper | View Slides\n  \nA P4-Based Content-Aware Approach to Mitigate Slow HTTP POST Attacks\nChih-Yu Hsieh (National Taiwan University)\, Hong-Yen Chen (National Taiwan University)\, Shan-Hsiang Shen (National Taiwan University of Science and Technology)\, Chen-Hsiang Hung (National Taiwan University)\, Tsung-Nan Lin (National Taiwan University)\nA slow HTTP POST attack is an application-layer distributed denial-of-service attack targeting web servers. The attacker simulates a legitimate user with a slow network speed and continues to send requests\, resulting in server resources being unavailable for a long time to other users. The similarity to legitimate behavior makes it challenging to identify such attack traffic. To address this issue\, this paper proposes a responsive defense mechanism that exploits programmable network devices to identify attack traffic based on HTTP headers. With information that is not available from legacy network devices\, this method can identify different types of requests and apply limitations. This approach achieves a distributed\, source-based defense capability by utilizing data plane programmability\, making it a scalable solution. The simulation results show that the approach is effective and accurate against slow HTTP POST attacks. \nRead Paper | View Slides\n  \nOn Implementing ChaCha on a Programmable Switch (Short Paper)\nYutaro Yoshinaka (Osaka University)\, Junji Takemasa (Osaka University)\, Yuki Koizumi (Osaka University)\, Toru Hasegawa (Osaka University)\nThis paper presents an implementation of a practical cryptographic primitive based on ChaCha on a Tofino programmable switch. A key challenge is optimizing the implementation by leveraging the structure of ChaCha operations and hardware features of Tofino. Our implementation outperforms the AES-based approach in terms of performance and small memory footprint and achieves up to 203 Gbps of throughput. \nRead Paper | View Slides\n\nSESSION: Architecture and Language\nReducing P4 Language’s Voluminosity using Higher-Level Constructs\nAlbert Gran Alcoz (ETH Zürich)\, Coralie Busse-Grawitz (ETH Zürich)\, Eric Marty (ETH Zürich)\, Laurent Vanbever (ETH Zürich) \nOver the last years\, P4 has positioned itself as the primary language for data-plane programming. Despite its constant evolution\, the P4 language still “suffers” from one significant limitation: the voluminosity of its code. Today\, P4 users overcome this limitation by relying on templating tools\, hand-crafted scripts\, and complicated macros. Unfortunately\, these methods are not optimal: they make the development process difficult and do not generalize well beyond one codebase. \nIn this work\, we propose reducing the voluminosity of P4 code by introducing higher-level language constructs. We present O4\, an extended version of P4\, that includes three such constructs: arrays (which group same-type entities together)\, loops (which reduce simple repetitions)\, and factories (which enable code parametrization).\nRead Paper | View Slides \nCompiling Packet Programs to dRMT Switches: Theory and Algorithms\nBalázs Vass (Budapest University of Technology and Economics)\, Ádám Fraknói (Eötvös Loránd University)\, Erika Bérczi-Kovács (Eötvös Loránd University)\, Gábor Rétvári (Budapest University of Technology and Economics) \nA critical step in P4 compilation is finding an efficient mapping of the high-level P4 source code constructs to the physical resources exposed by the underlying hardware\, while meeting data and control flow dependencies in the program. In this paper\, we take a new look at the algorithmic aspects of this problem\, with the motivation to understand the fundamental theoretical limits and obtain better P4 pipeline embeddings in the dRMT (disaggregated Match-Action Table) switch architecture. We report mixed results. We find that optimizing P4 program embedding for maximizing throughput is computationally intractable even when some architectural constraints are relaxed\, and there is no hope for a tractable approximation with arbitrary precision unless P = NP. At the same time\, we find that the maximal throughput embedding is approximable in quasi-linear time with a small constant bound. Our evaluations show that the proposed algorithm outperforms the heuristics of prior work both in terms of throughput and compilation speed. \nRead Paper | View Slides \n\n\n\nIn-Network Fractional Calculations using P4 for Scientific Computing Workloads \nShivam Patel (Illinois Institute of Technology)\, Rigden Atsatsang (Illinois Institute of Technology)\, Kenneth M Tichauer (Illinois Institute of Technology)\, Michael H L S Wang (Fermilab)\, James B Kowalkowski (Fermilab)\, Nik Sultana (Illinois Institute of Technology)\nRecent P4 research has motivated the need for in-network fractional calculations to support functions in Networking (for calculations related to active queue management and load balancing) and in Machine Learning. The P4 language and ASICs do not natively support fractional types (e.g.\, float). \n\nThis paper re-thinks the foundation of in-network fractional calculation and proposes a new approach that is more resource conscious and is straightforward to encode in P4. Instead of floating-point\, it uses a fixed-point encoding of numerals; and instead of sampling functions into tables it uses Taylor Approximation to reduce data-plane calculations to simple arithmetic over pre-calculated coefficients\, requiring constant space and linear time. The paper describes and evaluates a P4 code synthesis algorithm that allows users to trade-off switch resources for accuracy\, grounded on an application of a well-understood mathematical theory. It describes how to encode π and various functions including cos\, log and exp. \nRead Paper \nHOL4P4: Semantics for a Verified Data Plane \nAnoud Alshnakat (KTH Royal Institute of Technology)\, Didrik Lundberg (KTH Royal Institute of Technology\, Saab AB)\, Roberto Guanciale (KTH Royal Institute of Technology)\, Mads Dam (KTH Royal Institute of Technology)\, Karl Palmskog (KTH Royal Institute of Technology)\nWe introduce a formal semantics of P4 for the HOL4 interactive theorem prover. We exploit properties of the language\, like the absence of call by reference and the copy-in/copy-out mechanism\, to define a heapless small-step semantics that is abstract enough to simplify verification\, but that covers the main aspects of the language: interaction with the architecture via externs\, table match\, and parsers. Our formalization is written in the Ott metalanguage\, which allows us to export definitions to multiple interactive theorem provers. The exported HOL4 semantics allows us to establish machine-checkable proofs regarding the semantics\, properties of P4 programs\, and soundness of analysis tools. \nRead Paper | View Slides\n  \nSESSION: Monitoring and Applications\nCausal Network Telemetry \n\nYunhe Liu (Cornell University)\, Nate Foster (Cornell University)\, Fred B. Schneider (Cornell University)\nCurrent approaches to network observability rely on techniques like active probing\, packet sampling\, and path-level telemetry\, which only provide a partial view. This paper presents causal telemetry\, a new model that adapts ideas from distributed systems to the network setting. Causal telemetry captures causal relationships between events\, including those that take place on physically separated devices. We motivate causal telemetry through examples\, we show how it can be used to diagnose anomalies and faults\, and we present algorithms for constructing the needed causal graphs from network executions. We develop a P4-based prototype implementation\, CoCaTel\, and discuss a case study that uses causal telemetry to detect Priority-Based Flow Control (PFC) deadlocks. \nRead Paper | View Slides\n  \nInnovative network monitoring techniques through In-band Inter Packet Gap Telemetry (IPGNET)\nFrancisco Germano Vogt (University of Campinas)\, Fabricio Rodriguez (University of Campinas)\, Christian Esteve Rothenberg (University of Campinas)\, Gergely Pongrácz (Ericsson Research)\nNetwork monitoring is a fundamental task for proper network troubleshooting and performance management. Recently\, in-band Network Telemetry (INT) has been demonstrated as a powerful and efficient network monitoring framework. Using INT\, network information hop-by-hop can be collected directly from the data plane by gathering this information in the production traffic. However\, INT data collection is limited by available packet size and processing overhead\, making it critical to choose what data to collect and when to collect it. In this demo\, we propose the In-band Inter Packet Gap Network Telemetry (IPGNET) per-hop monitoring. We argue that by monitoring the IPG hop-by-hop\, it is possible to correlate the data and identify: (i) Network problems like congestion and delays\, finding their root cause\, and (ii) Microbursts and their contributing flows. Our preliminary results show that IPGNET can detect microbursts on multiple queues and report all the contributing flows with high efficiency in terms of control/data plane overhead. \n\nRead Paper\n  \nSketch-based Entropy Estimation: a Tabular Interpolation Approach Using P4 (Short Paper)\nYu-Kuen Lai (Chung-Yuan Christian University)\, Se-Young Yu (International Center for Advanced Internet Research)\, Iek-Seng Chan (Chung-Yuan Christian University)\, Bo-Hsun Huang (Chung-Yuan Christian University)\, Che-Hao Chang (National Taiwan University)\, Jim Hao Chen (International Center for Advanced Internet Research)\, Joe Mambretti (International Center for Advanced Internet Research)\nThis work presents the implementation of a tabular interpolation approach to estimate empirical Shannon entropy on programmable data plane ASICs using P4. The technique transforms the complex computations of the random projection into fast lookup over pre-computed tables in the match-action pipeline. Likewise\, the interpolation heuristic further reduces the table size substantially. Thus\, more tables can be accommodated\, achieving higher estimation accuracy. Simulations based on real-world network traffic traces are performed to evaluate the estimation accuracy. The scheme is deployed in a Barefoot Tofino2 switch connected to the International Center for Advanced Internet Research (iCAIR) national testbed. The system can estimate the entropy of network traffic accurately at 400 Gbps throughput. \nRead Paper\n  \nIn-network Angle Approximation for Supporting Adaptive Beamforming \nHiba Mallouhi (ELTE Eötvös Loránd University\, Budapest\, Hungary)\, Jaspreet Kaur (University of Glasgow)\, Hasan Tahir Abbas (University of Glasgow)\, Sándor Laki (ELTE Eötvös Loránd University\, Budapest\, Hungary)\nBeamforming is now an integral feature of modern wireless communication systems and its implementation calls for an accurate beam alignment by estimating the direction of signal arrival. However\, this estimation is computationally complex\, especially in a dynamic environment where a user is constantly on the move. In this paper\, we propose a user-assisted in-network method to optimally approximate the angle of arrival by segmenting the cell area into an exponentially binned grid and make use of the advantages offered by programmable data planes and their match-action table (MAT) logic. The proposed method is implemented in P4 and runs on a Tofino ASIC. Our evaluation proves a theoretical bound on the absolute error of the proposed MAT-based angle approximation and shows that it is in accordance with the empirical error distributions. \n\nRead Paper | View Slides \nDistributed DNN Serving in the Network Data Plane\nKamran Razavi (Technical University of Darmstadt)\, George Karlos (Vrije Universiteit Amsterdam)\, Vinod Nigade (Vrije Universiteit Amsterdam)\, Max Mülhäuser (Technische Universität Darmstadt)\, Lin Wang (Technische Universität Darmstadt\, Vrije Universiteit Amsterdam)\nThere is a great interest in utilizing P4 for in-network computing along with programmable data planes. This use is emerging as a new network paradigm that can not just reduce the complexity but the delay as well. Beamforming is now an integral feature of modern wireless communication systems and its implementation calls for an accurate beam alignment by estimating the direction of signal arrival. However\, this estimation is computationally complex\, especially in a dynamic environment where a user is constantly on the move.\nIn this paper\, we propose a user-assisted in-network method to optimally approximate the angle of arrival by segmenting the cell area into an exponentially binned grid and make use of the advantages offered by programmable data planes and their match-action table (MAT) logic. The method expects location messages periodically reported by user equipment\, processes them in the network and reconfigures the base station antennas accordingly\, implementing user-assisted in-network beam control. The proposed method is implemented in P4 and runs on a Tofino ASIC. \nRead Paper | View Slides\n\n  \n\n\n\nOrganizer Co-Chairs \n\nGianni Antichi\, Queen Mary University of London\nFernando Ramos\, University of Lisbon\n\nTPC Co-Chairs \n\nMarco Chiesa\, KTH Royal Institute of Technology\nShir Landau Feibish\, Open University of Israel\n\nPublicity Chair \n\nMarco Savi\, University of Milano-Bicocca\n\n\nProgram Committee \n\nAlan Zaoxing Liu (Boston University)\nAmedeo Sapio (Intel)\nBen Pfaff (VMware)\nDaehyeok Kim (Microsoft Research)\nDamu Ding (University of Oxford)\nGábor Rétvári (Budapest University of Technology and Economics)\nHyojoon Kim (Princeton University)\nMihai Budiu (VMware Research)\nMina Tahmasbi Arashloo (University of Waterloo)\nMuhammad Shahbaz (Purdue University)\nOri Rottenstreich (Technion)\nRoberto Bifulco (NEC Laboratories Europe)\nSalvatore Signorello (University of Lisbon)\nSándor Laki (Eötvös Loránd University)\nSimone Ferlin (Red Hat\, Karlstad university)\n\n\n\n\n\n 
URL:https://p4.org/event/euro-p4-2022/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20221205T080000
DTEND;TZID=UTC:20221205T080000
DTSTAMP:20260417T032036
CREATED:20250912T220223Z
LAST-MODIFIED:20250915T225653Z
UID:10000111-1670227200-1670227200@p4.org
SUMMARY:2022 P4 China Open Programmable Network Summit
DESCRIPTION:The 2022 P4 China Open Programmable Network Summit brings together experts\, scholars\, business executives\, and technical executives to discuss the practice\, development and trends of open programmable networks\, P4 languages\, and innovative applications of the network. Universities\, research institutes and companies in the academic salon will also share P4 scientific research experiences and collaboration. In addition\, the summit hosts an exhibition area. \nThe event is sponsored by Intel® and co-organizer\, Jiangsu Future Network Innovation Research Institute. \nThe Intel® 2022 P4 China Hackathon will be held in conjunction with the 2022 P4 China Open Programmable Network Summit. Learn more and register separately for this event. \n 
URL:https://p4.org/event/2022-p4-china-open-programmable-network-summit/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20221122T090000
DTEND;TZID=UTC:20221122T090000
DTSTAMP:20260417T032036
CREATED:20250912T220205Z
LAST-MODIFIED:20250915T225711Z
UID:10000109-1669107600-1669107600@p4.org
SUMMARY:P4 Workshop Taiwan
DESCRIPTION:The P4 Workshop Taiwan is being hosted by NYCU. Industry and academia speakers with extensive P4 experience will discuss P4 use cases and academic research projects. This event is free for attendees. \n09:00 – 09:10  Opening Ceremony\nJason Yi-Bing Lin\, Lifetime Chair Professor (NYCU\, Taiwan) \n09:10 – 09:40  Keynote: Intel Tofino Expandable Architecture Platform Acceleration Kits\nDaniel Alvarez\, Marketing Director\, Switch Fabric Group\, Intel \n09:40 – 10:10  Japan P4 Community Update and Use Cases\nKentaro Ebisawa\, Principal Researcher\, Toyota Motor Corporation \n10:10 – 10:30  Break \n10:30 – 11:00  P4-enabled 5G UPF QoS Enhancement and Network Slicing\nYu-Shen Liu\, Accton Technology Corporation \n11:00 – 11:30  Intel Infrastructure Processing Unit and IPDK Introduction\nHenry Sun\, Intel \n11:30 – 12:00  Speeding Up Network FPGA Design Using P4\nKai-Feng Chou\, Intel \n12:00 – 12:10  Lunch Time (Demo) \n13:10 – 13:40  P4 Testbed and Inter-Domain In-Band Telemetry\nTe-Lung Liu\, Research Fellow\, NARLABs\, Taiwan \n13:40 – 14:10  Mitigating New-Flow Attack with SDN Snapshot in P4-based SDN\nMeng-Hsun Tsai\, Associate Professor\, NCKU\, Taiwan \n14:10 – 14:40  Heterogeneous UPF Integration Framework and 5G User Plan Acceleration\nChien-Chao Tsent\, Professor\, NYCU\, Taiwan \n14:40 – 15:10  Break (Poster/Demo) \n15:10 – 15:30  Instant Queue Occupancy Used for Automatic Traffic Scheduling in Data Center Networks\nChien Chen\, Jointly Appointed Professor\, NYCU\, Taiwan \n15:30 – 15:50  Using a P4 Hardware Switch to Block Trackers and Ads for All Devices on an Edge Network\nShie-Yuan Wang\, Professor\, NYCU\, Taiwan \n16:00 – 16:30  Intel Broadband Network Gateway Acceleration Kit (Intel BNG Acceleration Kit)\nPetr Kastovsky\, Software Product Manager\, Intel
URL:https://p4.org/event/p4-workshop-taiwan/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20221118T080000
DTEND;TZID=UTC:20221118T080000
DTSTAMP:20260417T032036
CREATED:20250912T220223Z
LAST-MODIFIED:20250915T225716Z
UID:10000112-1668758400-1668758400@p4.org
SUMMARY:Intel® 2022 P4 China Hackathon
DESCRIPTION:The Intel® 2022 P4 China Hackathon aims to cultivate and discover outstanding P4 talents and help developers build network infrastructure\, machine learning and Applications in artificial intelligence\, high-performance computing\, network measurement and optimization\, network security and other scenarios will enhance the innovation ability of P4 developers and promote the construction of the P4 programmable network ecosystem.\n  \nThe Intel® 2022 P4 China Hackathon was initiated by Intel®\, ONF community initiative\, and co-organized by Jiangsu Future Network Innovation Research Institute. It is being held in conjunction with the P4 China Open Programmable Network Summit.
URL:https://p4.org/event/intel-2022-p4-china-hackathon/
CATEGORIES:Events
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DTSTART;TZID=UTC:20221024T080000
DTEND;TZID=UTC:20221024T080000
DTSTAMP:20260417T032036
CREATED:20250912T220222Z
LAST-MODIFIED:20250915T225723Z
UID:10000110-1666598400-1666598400@p4.org
SUMMARY:Netdev 0x16
DESCRIPTION:Netdev 0x16\, is a conference focused on Linux kernel networking and user space utilization of the interfaces to the Linux kernel networking subsystem are the focus.\nAs part of this event\, a hands-on workshop presented by P4 community members will take place\, “Learn How to Program the Linux Kernel Data Path with P4”. The session will offer an introduction to P4 programming with available open source software. The tutorial will feature a hands-on component where participants will learn how to program custom packet processing logic into the Linux kernel through several open source P4 technologies. \n  \nSpeakers: \nFernando Ramos\, Associate Professor\, Instituto Superior Superior Técnico\, University of Lisbon\nSalvatore Signorello\, Invited Assistant Professor at Faculdade de Ciências da Universidade de Lisboa
URL:https://p4.org/event/netdev-0x16/
CATEGORIES:Events
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DTSTART;TZID=UTC:20221020T080000
DTEND;TZID=UTC:20221020T080000
DTSTAMP:20260417T032037
CREATED:20250912T220224Z
LAST-MODIFIED:20250915T230820Z
UID:10000113-1666252800-1666252800@p4.org
SUMMARY:P4 Users Japan 2022
DESCRIPTION:The Japan P4 Users Group will be held as a hybrid event with both in-person and online access. This in-person event includes both presentations by industry and academic members of the P4 community who will share their use cases\, insights and experiences with P4. The event will also feature exhibits. \nIn addition to live sessions\, pre-recorded presentations will be released on the day of the event as well. \nCheck out the full agenda.
URL:https://p4.org/event/p4-users-japan-2022/
CATEGORIES:Events
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DTSTART;TZID=UTC:20220826T080000
DTEND;TZID=UTC:20220826T080000
DTSTAMP:20260417T032037
CREATED:20250912T220204Z
LAST-MODIFIED:20250915T230826Z
UID:10000107-1661500800-1661500800@p4.org
SUMMARY:ACM SIGCOMM 2022
DESCRIPTION:Hackathon: P4 on Raspberry PI for Networking Education\nAugust 26th | 1:30pm – 6:00pm\n \nP4Pi is a low cost\, open source hardware platform intended for teaching and research purposes. P4Pi enables designing and deploying P4-based network devices using the Raspberry Pi board. By setting a target price tag of less than an academic book (under $100)\, P4Pi aims to enable a large number of academic institutes to provide hands-on experience in networking education. Furthermore\, as P4Pi is based on the popular Raspberry PI platform\, it appeals to other communities such as hobbyists and does not depend on a single-source provider. \nP4Pi is developed as part of the P4 Education Workgroup activities. The team aims to provide both educators and practitioners the knowledge and tools required to use P4Pi in class and at home\, including tutorials\, sample code\, tools and community support. \nThis hackathon aims to bring together members of the networking community for the following goals: (i) introduce P4Pi to networking researchers and educators\, enable them to get started with the platform and practice its use in lab-like environment. (ii) develop more teaching and supporting materials for the P4Pi ecosystem. (iii) enable researchers from all levels of expertise to develop P4Pi-based concepts and early-stage projects\, and to stimulate collaborations between new users. \nCheck out all the details here!
URL:https://p4.org/event/acm-sigcomm-2022/
CATEGORIES:Events
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DTSTART;TZID=UTC:20220524T080000
DTEND;TZID=UTC:20220526T080000
DTSTAMP:20260417T032037
CREATED:20250912T220203Z
LAST-MODIFIED:20250915T230839Z
UID:10000105-1653379200-1653552000@p4.org
SUMMARY:P4 2022 Workshop
DESCRIPTION:The P4 2022 Workshop incorporates insights and perspectives from P4 community members around the world and encompass topics related to: \n\nP4 language\nP4 compile targets\nP4 tool chain\nP4 use cases & apps\nControl plane or network OS for P4 targets\n\nCheck out all the talks from this exciting and informative event on-demand below! Or\, view full YouTube playlist. \n  \n\n\n\nKeynotes\n\n\n\n\n\nTITLE\nVIDEO\nSLIDES\n\n\n\n\n\n\nWelcome to P4 Workshop 2022!\nJK Lee\, Program Chair\, member of P4 TST\, Senior Principal Engineering\, Intel\n\n\n\n\n\n\n\nP4 on the Move!\nAndy Fingerhut\, Principal Engineer\, Intel\n\n\n\n\n\n\n\n\nProgrammable Network Devices: One Vendor’s Perspective\nKenneth Duda\, Founder\, CTO & SVP Software Engineering\, Arista Networks\n\n\n\n\n\n\n\nPanel – IPU/DPU\nBrad Burres\, Fellow\, Intel\nMatty Kadosh\, Principle Architect\, Nvidia\nKrishna Doddapaneni\, Co-founder\, VP Software Engineering\, Pensando\nGordon Brebner\, Senior Fellow\, AMD\n\n\n\n\n\n\n\nScaling SDN Policy Distribution\nBen Pfaff\, Principal Researcher\, VMware\n\n\n\n\n\n\n\nExpanding the P4 Universe\nGordon Brebner\, Senior Fellow\, AMD\n\n\n\n\n\n\n\n\nProgrammable Networking for a Distributed Edge\nNick McKeown\, SVP & GM and Senior Fellow\, Network & Edge Group\, Intel\nSachin Katti\, CTO\, Network & Edge Group\, Intel\n\n\n\n\n\n\n\n\nThe Journey Towards Predictable Network in Alibaba Cloud\nDennis Cai\, Head of Network Infrastructure\, Alibaba\n\n\n\n\n\n\n\n\nSONiC\, Programmability & Acceleration\nXin Liu\, Principal Product Manager\, Microsoft\n\n\n\n\n\n\n  \n\n\nLanguage\n\n\n\n\n\nTITLE\nVIDEO\nSLIDES\n\n\n\n\n\n\nExtend P4 to Support Runtime Programmability – In Depth Talk\nYong Feng\, Ph.D Student\, Tsinghua University\nDr. Haoyu Song\, Researcher\, Futurwei Technologies\n\n\n\n\n\n\n\n\nApplets\, a Portability and Composability Solution for P4 – In Depth Talk\nVenkat Pullela\, Chief of Technology\, Networking\, Keysight\nSurendra Anubolu\, Distinguished Engineer\, Broadcom\n\n\n\n\n\n\n\n\nPrimitives for Finite Field Arithmetic in Network Switches – In Depth Talk\nDaniel Seara\, MSc Student\, IST\, Universit of Lisbon\nBernardo Conde\, Master Student\, IST\, Universit of Lisbon\n\n\n\n\n\n\n\n\nNERPA: Network Programming with Relational and Procedural Abstractions – In Depth Talk\nDebnil Sur\, Senior Software Engineer\, VMware\n\n\n\n\n\n\n\n\nSuperP4: Preprocessor-Aware Syntax and Semantic Analysis for P4 Programs – Tech Brief\nKaarthik Alagappan\, Graduate Research Assistant\, University of Central Florida\n\n\n\n\n\n\n\n\nP4RROT: Generating P4 Code for the Application Layer – Tech Brief\nCsaba Györgyi\, PhD Student\, ELTE Eötvös Loránd University\nSandor Laki\, Assitant Professor\, ELTE Eötvös Loránd University\n\n\n\n\n\n\n\n  \n\n\n\n\n\nTarget\n\n\n\n\n\nTITLE\nVIDEO\nSLIDES\n\n\n\n\n\n\nConnection Tracking Using P4 – In Depth Talk\nAnjali Singhai Jain\, Principle Engineer\, Intel\nNishanth Bhat\, Intel\nNamrata Limaye\, Intel\n\n\n\n\n\n\n\n\nSpeeding Up Network FPGA Design Using P4 – In Depth Talk\nBert Klaps\, Senior Systems Engineer\, Intel\nMiroslaw Walukiewicz\, Intel\n\n\n\n\n\n\n\n\nLine Rate IPsec on a PNA-Compliant Packet Processing Pipeline – In Depth Talk\nSameer Kittur\, Distinguished Engineer\, Pensando Systems\n\n\n\n\n\n\n\n\nP4 Over Linux TC – In Depth Tal\nJamal Hadi Salim\, CEO\, Mojatatu Networks\n\n\n\n\n\n\n\n\nDevelop Your CPU Network Stack in P4 – In Depth Talk\nCristian Dumitrescu\, Software Architect for Packet Processing\, Intel\n\n\n\n\n\n\n\n\nP4 at the Interface Between NIC and Host – In Depth Talk\nRaghava Sivaramu\, Fellow\, Pensando Systems\n\n\n\n\n\n\n\nP4 in Open vSwitch with OfP4 – Tech Brief\nBen Pfaff\, Researcher\, VMware\n\n\n\n\n\n\n\nDeep Dive & Getting Started with PSA Implementation for eBPF – Tutorial\nTomasz Osiński\, Cloud Software Development Engineer\, Intel\nMateusz Kossakowski\, R&D Expert\, Orange Labs Poland\nJan Palimaka\, Chief R&D Specialist\, Orange Labs Poland\n\n\n\n\n\n\n\n\nPSA-eBPF: Portable Switch Architecture for eBPF – Tech Brief\nTomasz Osiński\, Cloud Software Development Engineer\, Intel\nMateusz Kossakowski\, R&D Expert\, Orange Labs Poland\nJan Palimaka\, Chief R&D Specialist\, Orange Labs Poland\n\n\n\n\n\n\n\n\n\nTool Chain\n\n\n\n\n\nTITLE\nVIDEO\nSLIDES\n\n\n\n\n\n\np4testgen: Automated Test Generation for Real-World P4 Data Planes – In Depth Talk\nFabian Ruffy\, Intern\, Intel and PhD Student\, NYU\n\n\n\n\n\n\n\nDynamic P4 Pipeline Configuration – In Depth Talk\nAnjali Singhai Jain\, Principle Engineer\, Intel\nHari Thantry\, Cloud Architect\, Google\n\n\n\n\n\n\n\n\nDifferential Testing of P4 Implementations Using CI/CD – Tech Brief\nParisa Ataei\, Postdoc Scholar\, Cornell University\n\n\n\n\n\n\n\n\nP4 Designer – Demo\nPratap Pellakuru\, Development Tools Software Architect\, Intel\nSharmila S.\, Cloud Software Development Engineer\, Intel\n\n\n\n\n\n\n\n\nIntroducing IPDK – Tutorial\nDeb Chatterjee\, Senior Director of Engineering\, Intel\n\n\n\n\n\n\n\n\n\nControl Plane and NOS\n\n\n\n\n\nTITLE\nVIDEO\nSLIDES\n\n\n\n\n\n\nEvolving P4 Runtime From Switch to DPU – In Depth Talk\nMilind Chabbi\, Nvidia\nAlan Lo\, Compiler/Cloud Architect\, Nvidia\n\n\n\n\n\n\n\n\nAccelerating 5G (Mobile Core) Control Plane Using P4 – In Depth Talk\nJingqi Huang\, Ph.D Student\, Purdue University\nJiayi Meng\, PhD Candidate\, Purdue University\n\n\n\n\n\n\n\nTable Driven Interface (TDI): Usages and Advantages – In Depth Talk\nSayan Bandyopadhyay\, Cloud Software Developer\, Intel\nJames Choi\, Cloud Software Architect\, Intel\n\n\n\n\n\n\n\nPINS Update and Roadmap – In Depth Talk\nBhagat Janarthanan\, Software Engineering Lead\, Google\nBrian O’Connor\, Intel\nVamsi Punati\, Google\nReshma Sudarshan\, Director of Applications Engineering\, Intel\n\n\n\n\n\n\n\nPINS Packet I/O – In Depth Talk\nSrikishen Pondicherry\, Software Engineer\, Google\nBrian O’Connor\, Intel\nDon Newton\, Intel\n\n\n\n\n\n\n\nP4-OVS Split Architecture – In Depth Talk\nNamrata Limaye\, Engineering Manager/Tech Lead\, Intel\nBrian O’Connor\, Intel\nAjay Kumar Dubey\, Intel\n\n\n\n\n\n\n\nP4 as a Single Source of Truth for SONiC DASH Use Cases on Both Softswitch and Hardware – In Depth Talk\nReshma Sudarshan\, Director of Applications Engineering\, Intel\nChris Sommers\, Sr. Software Architect\, Keysight\n\n\n\n\n\n\n\nPINS Getting Started – Tutorial\nJudy Snow\, ONF\nBrian O’Connor\, Intel\n\n\n\n\n\n\n\n\nApplication\n\n\n\n\n\nTITLE\nVIDEO\nSLIDES\n\n\n\n\n\n\nP4 FOR NIC – A CLOUD PROVIDER PERSPECTIVE – In Depth Talk\nHari Thantry\, Cloud Architect\, Google\n\n\n\n\n\n\n\nInband Network Telemetry (INT): History\, Impact and Future Directions – In Depth Talk\nJK Lee\, Sr. Principal Engineer\, Intel\nMukesh Hira\, Principal Engineer\, Networking and Security\, VMware\n\n\n\n\n\n\n\nNetwork Programmability “Squared” – In Depth Talk\nSatoru Matsushima\, Technical Meister\, Softbank\n\n\n\n\n\n\n\nArchitecture for Multi-Terabit Programmable Networking Functions – In Depth Talk\nPetr Kastovsky\, Product Marketing\, Intel\nGeorgios Nikolaidis\, Software Architect\, Intel\n\n\n\n\n\n\n\nA Change Detection Primitive for the Network Data Plane – In Depth Talk\nGonçalo Matos\, Researcher\, INESC-ID\n\n\n\n\n\n\n\nM-PolKA: Enabling and Exploiting Multipath Stateless Source Routing for Programmable Data Planes – In Depth Talk\nRafael S. Guimaraes\, Associate Professor\, Instituto do Espirito Santo\n\n\n\n\n\n\n\nPMNet: In-Network Data Persistence – In Depth Talk\nKorakit Seemakhupt\, Graduate Student\, University of Virginia\n\n\n\n\n\n\n\nService Mesh P4 Data Plane – In Depth Talk\nAnjali Singhai Jain\, Principle Engineer\, Intel\nMrittika Ganguli\, Intel\nValas Valancius\, Google\nNupur Jain\, Intel\n\n\n\n\n\n\n\nTowards In-Network Anomaly Detection – In Depth Talk\nJoão Romeiras Amado\, PhD Student\, INESC-ID\, University of Lisbon\n\n\n\n\n\n\n\nDemo of L2 Forwarding + Vxlan with Control Packet Flow Using P4-OVS – Demo\nNupur Uttarwar\, Cloud Software Engineer\, Intel\nSandeep Nagapattinam\, Cloud Software Engineer\, Intel\n\n\n\n\n\n\n\nP7 (P4 Programmable Patch Panel): An Instant 100G Emulated Network Testbed in a Pizza Box – Demo\nFabricio Rodriguez\, PhD Student\, UNICAMP\n\n\n\n\n\n\n\nEnabling WCMP in SONiC Using PINS and ONOS – Demo\nNillofar Toorchi\, MTS\, ONF\nDaniele Moro\, Cloud Software Development Engineer\, Intel\n\n\n\n\n\n\n\nTCP-INT: Lightweight INT in TCP Transport – Demo\nSimon Wass\, Cloud Software Engineer\, Intel\nMiao Mao\, Staff Software Engineer\, Baidu\n\n\n\n\n\n\n\nOpen SRv6 Project: Open Source for P4-based Edge Router – Demo\nWeiqiang Cheng\, Principle Architect of IP Network\, China Mobile\nJiang Liu\, Professor\, Beijing University of Posts and Telecommunications\n\n\n\n\n\n\n\nPath Tracing: Revealing the Unknowns about ECMP – Demo\nAhmed Abdelsalam\, Software Engineer\, Cisco Systems\n\n\n\n\n\n\n\nSD-Fabric (Part 1) – Tutorial\nCarmelo Cascone\, Cloud Software Development Engineer\, Intel\nCharles Chan\, Cloud Software Development Engineer\, Intel\n\n\n\n\n\n\n\nSD-Fabric (Part 2) – Tutorial\nCarmelo Cascone\, Cloud Software Development Engineer\, Intel\nCharles Chan\, Cloud Software Development Engineer\, Intel\n\n\n\n\n\n\n\nSD-Fabric (Part 3) – Tutorial\nCarmelo Cascone\, Cloud Software Development Engineer\, Intel\nCharles Chan\, Cloud Software Development Engineer\, Intel
URL:https://p4.org/event/p4-2022-workshop/
CATEGORIES:Events
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