P4 Developer Days - In-Network Inference with P4: From Stateless to Hybrid Approaches
2026-01-21 08:00 UTC
Register to attend this P4 Developer Days webinar, “In-Network Inference with P4: From Stateless to Hybrid Approaches”
Date: January 21, 2026
Time: 8:00am Pacific
Abstract
In-network machine learning (ML) techniques employ the P4 language to embed trained ML models directly into programmable network data planes. This has enabled novel applications in network security, routing optimization, and traffic classification, amongst others. This presentation charts the evolution of these techniques, starting with stateless, packet-level inference models like Henna. It then explores the shift to stateful, flow-level approaches as demonstrated in Flowrest. The talk culminates with Jewel, a novel hybrid system that performs joint packet and flow-level inference for improved accuracy and efficiency. This journey from stateless to hybrid methodologies highlights the advancements and trade-offs in building intelligent, high-performance, and ML-empowered networks with P4.

Speaker
Aristide Akem is a Lecturer in Computer Science within the Cyberphysical Systems Group in the School of Electronics and Computer Science at the University of Southampton. Before joining Southampton, he was a postdoctoral researcher in the Computing Infrastructure Group at the University of Oxford. His research spans machine learning, network programming with P4, and mobile networking, with applications in network security, IoT, and energy. He earned his PhD from Universidad Carlos III de Madrid and IMDEA Networks Institute, following a Master of Science in Electrical and Computer Engineering from Carnegie Mellon University Africa, and a Master’s in Telecommunications Engineering from the University of Yaounde I.

P4 Developer Days - Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA based SmartNICs
2026-02-04 08:00 - 09:00
Register to attend this P4 Developer Days webinar, “Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA-based SmartNICs”

Date: February 4, 2026
Time: 8:00am Pacific
Abstract
The exponential growth of cloud-native services, 5G connectivity, and data-intensive applications is driving unprecedented demand for high-throughput and flexible packet processing. Traditional fixed-function ASIC solutions, while performant, lack the adaptability to address emerging tunnelling protocols, dynamic QoS enforcement, and evolving custom workloads. P4, an open and protocol-independent programming language for the data plane, directly addresses these limitations by enabling developers to rapidly define and deploy advanced packet pipelines without RTL complexity. By combining FPGA Vendors P4 Compilers like Altera’s P4 Suite with iW-Fibre SmartNICs, operators can synthesize programmable pipelines that sustain line-rate performance while remaining fully adaptable.
Demonstration of the use cases – including checksum verification, IP-in-IP tunnelling, VXLAN encapsulation/decapsulation, and standards-based QoS metering—illustrate how P4 empowers service providers and data centers to stay agile, scalable, and future-ready.
Speaker
Chethan T V is an Electronics an Communications Engineer possessing diverse experience in embedded industry as a digital design engineer with extensive expertise in FPGA design flow and SoC lifecycle. With strong project management skills, he has led various challenging projects from conceptualization stage to execution and delivered successful products in the field of defense, video, military & commercial sectors. He is an Associate Director, FPGA BU, iWave Global – leading the Smart-NIC division from the ground up, building a high-performing team, and driving strategic projects in next-generation networking.

P4 Developer Days - P4Muse (P4 Modularity and Unification for Seamless Extensibility)
2026-03-04 08:00 - 09:00
Register to attend this P4 Developer Days webinar, “P4Muse (P4 Modularity and Unification for Seamless Extensibility”
Date: March 4, 2026
Time: 8:00am Pacific
Abstract

Domain-specific programming languages such as P4 enable flexible and high-performance packet processing in programmable network data planes. However, most P4 programs remain monolithic, limiting the development of modular and reusable protocols and libraries. Introducing modularity to P4 has been challenging because existing approaches—such as trans-compilers and virtualization—operate outside the P4 language and compiler, reducing backward compatibility and extensibility. P4Muse (P4 Modularity and Unification for Seamless Extensibility) addresses this challenge by introducing a compiler-managed approach to modularity within the P4C compiler. Without requiring any new syntax or annotations, P4Muse introduces new compiler passes for automatic code merging, enabling modular design, reuse, and seamless integration of complex network functionalities. Our results show that P4Muse effectively supports modular P4 program development without altering existing P4 syntax, providing a robust solution that significantly improves code reusability, flexibility, and extensibility while maintaining backward compatibility.

Speakers
Mohsen Rahmati is a Ph.D. candidate in Computer Engineering at Polytechnique Montréal, supervised by Professors Yvon Savaria, François-Raymond Boyer, and Jean-Pierre David. His research focuses on compiler design for programmable networks, emphasizing modularity and reusability in the P4 language. He is the creator of P4Muse, a compiler-managed modularity framework (accepted in IEEE Access, 2025), and P4O2, an object-oriented-inspired modularity in P4 currently under review at IEEE Access.

François-Raymond Boyer received B.Sc. and Ph.D. degrees in computer science from Université de Montréal, Montreal, QC, Canada, in 1996 and 2001, respectively. Since 2001, he has been with Polytechnique Montréal, Montréal, where he is currently a Professor with the Department of Computer and Software Engineering. He has authored or co-authored more than 30 conference and journal papers. His current research interests include microelectronics, performance optimization, parallelizing compilers, digital audio, and body motion capture. He is a member of Regroupement Stratégique en Microélectronique du Québec, Groupe de Recherche en Microélectronique et Microsystèmes, and Observatoire Interdisciplinaire de Création et de Recherche en Musique.
