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X-WR-CALDESC:Events for P4 - Language Consortium
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BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260520T080000
DTEND;TZID=America/Vancouver:20260520T090000
DTSTAMP:20260521T135336Z
CREATED:20260310T142654Z
LAST-MODIFIED:20260521T135336Z
UID:10000157-1779264000-1779267600@p4.org
SUMMARY:P4 Developer Days – EdgeP4: In-Network Edge Intelligence for a Tactile Cyber-Physical System Testbed Across Cities
DESCRIPTION:Register to attend this P4 Developer Day webinar on May 20 at 11 am ET/5 pm CET \nEdgeP4: In-Network Edge Intelligence for a Tactile Cyber-Physical System Testbed Across Cities\nSlides (PDF) | Watch Recording \n\n\nAbstract\nTactile Internet based operations\, e.g.\, telesurgery\, rely on the human operator for end-to-end closed loop control to achieve accuracy. While feedback and control are subject to network latency and packet loss\, critical operations such as pose correction\, fiducial marking\, tremor reduction\, etc. are tasks that should be carried out automatically and thus dispensing with these feedback signals from traversing the network to the other end. We designed two edge intelligence algorithms hosted at P4 programmable end switches placed 400 km apart. These algorithms locally compute and command corrective signals. We implement these algorithms entirely on the data plane on Netronome Agilio SmartNICs. “pose correction” is placed at the edge switch connected to an industrial robot gripping a tool. \nThe round trip between transmitting force sensor array readings to the edge switch and receiving correct tip coordinates at the robot is shown to be less than 100µs. “tremor suppression” is placed at the edge switch connected to the operator. It suppresses physiological tremors\, which improves the application’s performance and also reduces the network load up to 99.9%. Our EdgeP4 framework allows edge intelligence modules to seamlessly switch between the algorithms based on the tasks being executed by devices connected to their ports. \n\nSpeaker\nDeepak Choudhary is currently a master’s student and a research assistant at Aalto University\, Finland. His research interests primarily lie in Systems and Networking\, specifically in software-defined networking and programmable data planes. Previously\, he spent 2.5 years as a research assistant at the Indian Institute of Science (IISc). His work there focused on developing a P4-programmable Time-Sensitive Networking (TSN) switch and testing them on wide-area network testbeds. \n\nRegister to attend this virtual & free event
URL:https://p4.org/event/edgep4-may20/
CATEGORIES:Events
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260610T080000
DTEND;TZID=America/Vancouver:20260610T090000
DTSTAMP:20260611T135717Z
CREATED:20260428T123842Z
LAST-MODIFIED:20260611T135717Z
UID:10000160-1781078400-1781082000@p4.org
SUMMARY:P4 Developer Days – A Multi-Site Testbed for Heterogeneous P4 Data Plane Experimentation on Research Cyberinfrastructure
DESCRIPTION:Register to attend this P4 Developer Day webinar on June 10 at 11 am ET/5 pm CET \nSlides (PDF) | Watch Recording \nA Multi-Site Testbed for Heterogeneous P4 Data Plane Experimentation on Research Cyberinfrastructure\n\n\nAbstract\nThis presentation introduces a multi-site testbed that unifies three distinct classes of P4-programmable hardware\, FPGA SmartNICs (AMD Alveo)\, DPUs (NVIDIA BlueField)\, and software switches (BMv2)\, under a single Kubernetes control plane on the National Research Platform (NRP). We detail the architecture that uses ESnet’s SENSE orchestrator for dynamic multi-domain Layer 2 path provisioning and a unified shell automation framework for reproducible experiments. We also share critical lessons learned from integrating heterogeneous targets and running a real-world deployment. This work provides a blueprint for building and operating advanced\, reproducible P4 experimentation infrastructure for the research community. \nSpeaker\nMohammad Firas Sada is a researcher at SDSC specializing in deep learning\, high-performance computing (HPC)\, and advanced networking. His work within the Nautilus Kubernetes cluster at the National Research Platform focuses on distributed AI workflows\, network programmability\, hardware acceleration with novel compute architectures\, and scalable cyberinfrastructure for data-intensive science. His interests include optimizing AI training across GPU clusters\, accelerating scientific computing with programmable networks\, and developing tools for large-scale data movement and workflow automation. He enjoys working with talented teams to foster collaboration\, exchange ideas\, and advance research in computing. \n\n\nRegister to attend this virtual & free event
URL:https://p4.org/event/p4-data-plane/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=UTC:20260612T070000
DTEND;TZID=UTC:20260612T083000
DTSTAMP:20260602T134124Z
CREATED:20260602T134048Z
LAST-MODIFIED:20260602T134124Z
UID:10000163-1781247600-1781253000@p4.org
SUMMARY:P4 GSoC 2026 || Kickoff Meeting
DESCRIPTION:Join us for the 2026 P4 GSoC Kickoff Meeting. Request Meeting Invite here to join \nOur 5 project contributors will present what they will work on between June and August 2026. \nHere are the five accepted projects: \n\nPolyglot P4TC: Python and Rust API Wrappers for Linux TC-based P4\n\nContributor: Attaullah Ansari\, Birla Institute of Technology\, Mesra\n\n\nBMv2 packet trace support\n\nContributor: Yuao Ma\, Huazhong University of Science and Technology\n\n\nImproving The Traffic Manager of the P4Sim Switch\n\nContributor: Vineet Goel\, Indian Institute of Technology Roorkee\n\n\nEnhancing P4-SpecTec Usability: A Mechanized Specification for Nano-P4\n\nContributor: Haechan Kwon\, Korea Advanced Institute of Science & Technology\n\n\nIntegrating P4 Based In Network Machine Learning Framework into P4Pi\n\nContributor: Yuzhong (WeiWei) Luo\, University of Oxford\n\n\n\nRead more
URL:https://p4.org/event/p4-gsoc-2026-kickoff-meeting/
CATEGORIES:Events
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260625T080000
DTEND;TZID=America/Vancouver:20260625T090000
DTSTAMP:20260626T150633Z
CREATED:20260430T135723Z
LAST-MODIFIED:20260626T150633Z
UID:10000161-1782374400-1782378000@p4.org
SUMMARY:P4 Developer Days –  P4Check: a P4 Verification Tool
DESCRIPTION:Register to attend this P4 Developer Day webinar on June 25 at 8 am PT/11 am ET/5 pm CET \nSlides (PDF) | Watch Recording \nP4Check: a P4 Verification Tool\n\n\nAbstract\nWe present P4Check\, a scalable and practical one-stop shop for verifying data planes defined in P4. P4Check combines well-proven techniques\, symbolic execution\, big-step semantics and model checking with a novel high-level specification language into a tool to verify properties of stateful P4 programs at both the device and network levels. We present case studies showing property verification and bug detection for real-world P4 programs and conduct experiments to quantify the performance of P4Check compared to earlier works. \nSpeaker\nTommaso Pacciani is a PhD candidate in Multiscale Networked Systems (MNS) at the University of Amsterdam. His research focuses on applying formal methods and language design to enable the verification of programmable networks. His additional research interests include functional programming\, effect systems\, and debugging. \n\n\nRegister to attend this virtual & free event
URL:https://p4.org/event/p4check/
CATEGORIES:Events
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260709T080000
DTEND;TZID=America/Vancouver:20260709T090000
DTSTAMP:20260710T155728Z
CREATED:20260428T130542Z
LAST-MODIFIED:20260710T155728Z
UID:10000162-1783584000-1783587600@p4.org
SUMMARY:P4 Developer Days – MORP4: A Dynamic Network Telescope
DESCRIPTION:Register to attend this P4 Developer Day webinar on July 9 at 9 am PT/11 am ET/5 pm CET \nSlides | Watch Recording \nMORP4: A Dynamic Network Telescope\n\n\nAbstract\nA network telescope passively monitors unsolicited traffic reaching unused Internet address space advertised to the global routing system. For more than two decades\, network telescopes have allowed unique global visibility into a wide range of Internet phenomena. However\, telescopes are afflicted by two main issues: progressive erosion due to IPv4 space unavailability and blacklisting. To overcome these issues\, we propose MORP4\, a programmable data-plane framework implementing a “dynamic” network telescope. \nMORP4 accurately and adaptively tracks unused space of an organization’s network with configurable time and space granularity and captures only traffic directed towards unused addresses at line rate. We provide an implementation in P4 and Python/C++\, and deploy it on a Tofino switch. We show that it can detect unused IPv4 address space at the finest granularity (/32) while operating at line rate and provide an effective approach for operating a telescope in the IPv6 domain. \nSpeaker\nIliana Xygkou is a fourth-year PhD student in Computer Science at Georgia Tech\, supervised by Prof. Dainotti. Her research focuses on interdomain routing security and Internet measurements. She holds a Diploma in Electrical and Computer Engineering from the National Technical University of Athens. Iliana is particularly interested in detecting and analyzing BGP routing anomalies and conducting network telescope measurements with the use of programmable switches. Her work aims to shed more light on current trends in misconfigurations and attacks in both the control and data planes. Iliana is also a recipient of the Onassis Foundation Scholarship. \n\n\nRegister to attend this virtual & free event
URL:https://p4.org/event/morp4/
CATEGORIES:Events
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260812T080000
DTEND;TZID=America/Vancouver:20260812T090000
DTSTAMP:20260722T145400Z
CREATED:20260722T145400Z
LAST-MODIFIED:20260722T145400Z
UID:10000168-1786521600-1786525200@p4.org
SUMMARY:P4 Developer Days – High-Performance Traffic Management: Building a Multi-Layer HCoS Router with P4
DESCRIPTION:High-Performance Traffic Management: Building a Multi-Layer HCoS Router with P4\n\n\nAbstract\nThe Hierarchical Quality of Service (is a very important topic in networking and integrated part of routers. There are few methods used to implement it in hardware in a programmable way possible with P4. The P4 language generally does not define HQoS as a language feature. Instead use the P4 may help defining flexibility in various QoS models implementations. \nThe presentation shows the hardware extern model based on a sorting engine when connected with P4 creates an opportunity to implement complex scheduling algorithms. Also\, the more advanced HQoS topics related to flexible scheduling based on timestamps are covered allowing implementation of TSN protocol families. \nSpeaker\nMirek Walukiewicz is a Principal Engineer in Pantherun Technologies. He has 33 years of experience in networking technology and is currently a Solution Architect working with customers on P4 integration with FPGA products. He works on complex use-cases related to traffic scheduling in custom switches and routers\, time synchronization and Time Sensitive Networking. \n\n\n🗓️ [Click here] to add event and zoom details to your calendar for August 12 at 8 am PT (virtual & free)
URL:https://p4.org/event/multi-layer-hcos-router-with-p4/
CATEGORIES:Events
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Denver:20260817T090000
DTEND;TZID=America/Denver:20260817T130000
DTSTAMP:20260721T100839Z
CREATED:20260715T155632Z
LAST-MODIFIED:20260721T100839Z
UID:10000165-1786957200-1786971600@p4.org
SUMMARY:SIGCOMM 2026 | Programming SmartNICs Tutorial
DESCRIPTION:ACM SIGCOMM is the flagship annual conference of the ACM Special Interest Group on Data Communication (SIGCOMM). ACM SIGCOMM 2026\, the 40th edition of the conference series\, will be held between August 17 – 21\, 2026\, at the Colorado Convention Center in Denver\, Colorado\, USA. \nDon’t miss this tutorial by P4 community members at the event on August 17. \nProgramming SmartNICs: From Packet Processing to Programmable Transport \nProgrammable switches transformed networking research by making the data plane accessible and programmable. A similar shift is now happening at the network edge: SmartNICs\, DPUs\, and IPUs are evolving into programmable computing platforms capable not only of packet processing\, but also of stateful services and transport-layer functionality. Rather than being fixed-function offload devices\, they are becoming heterogeneous subsystems tightly integrated with host software stacks. \nThis tutorial provides a unified\, systems-oriented introduction to SmartNIC programmability\, spanning four tightly coupled dimensions: data-plane packet processing\, stateful network function design\, transport-layer programmability\, and host-level integration. It combines conceptual foundations with guided hands-on exercises on NVIDIA BlueField platforms using NVIDIA Launchpad\, allowing participants to gain both architectural understanding and practical experience with packet-processing and transport programmability. \nBy the end of the tutorial\, attendees will understand the design space across SmartNIC\, DPU\, and IPU platforms; write and deploy packet-processing logic on NIC targets; design and evaluate stateful services; experiment with transport-layer customization and programmable congestion control; and integrate NIC-based functionality with host control planes and software stacks. \nSpeakers:  \n\nFernando Ramos INESC-ID\, IST\, University of Lisbon\nMuhammad Shahbaz\, University of Michigan\nMina Tahmasbi Arashloo\, University of Waterloo\nMario Baldi\, NVIDIA\n\nView tutorial details \nTutorial Schedule\n08:30 – 09:15: SmartNIC Architectures and Programming Models\nSmartNIC/DPU/IPU architectures; match-action pipelines vs. programmable cores vs. FPGA; Portable NIC Architecture (PNA); packet processing vs. transport programmability. \n09:15 – 09:45: Packet Processing Programming on SmartNICs\nTable lookups; packet transformations; control-plane integration.Programming with P4\, DOCA Pipeline Language (DPL) and DOCA Flow. \n09:45 – 10:15: Transport Programming on SmartNICs\nProgrammable congestion control; transport-layer extensions; host-NIC coordination; open research challenges. \n10:15 – 10:45: Break \n10:45 – 11:30 Hands-On I: Programming the SmartNIC Packet Pipeline\nHands-on development of packet-processing functionality\, including forwarding\, filtering\, table lookups\, and packet transformations\, on BlueField-3 using DPL (DOCA Pipeline Language) and DOCA Flow to program the packet processing pipeline of the ConnectX-7 component. \n11:15 – 12:15: Hands-On II: Transport Programmability on SmartNICs\nHands-on experimentation with programmable transport functionality using DOCA PCC (Programmable Congestion Control) and DPA (Data Path Accelerator) execution on BlueField-3; evaluating transport behavior and host-NIC interaction.
URL:https://p4.org/event/sigcomm-2026-programming-smartnics-tutorial/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260924T080000
DTEND;TZID=America/Vancouver:20260924T090000
DTSTAMP:20260716T145856Z
CREATED:20260716T145834Z
LAST-MODIFIED:20260716T145856Z
UID:10000166-1790236800-1790240400@p4.org
SUMMARY:P4 Developer Days – Securing P4 Programs by Information Flow Control
DESCRIPTION:Securing P4 Programs by Information Flow Control\n\n\nAbstract\nP4’s flexibility makes it easy to leak sensitive data without realizing it. A bad table entry\, a copy-paste bug in a branch condition\, or a stray debug field can quietly expose secrets to an untrusted network\, and nothing in the toolchain today catches it. \nI’ll show how our tool\, TAP4S\, catches this kind of leak automatically. You mark which fields are sensitive and which ports are untrusted\, and it checks every path for violations\, with no annotations or code changes required. \nSpeaker\nAnoud Alshnakat is a PhD researcher in Formal Methods at KTH Royal Institute of Technology in Stockholm\, where her work focuses on verifying and securing P4 data-plane programs (HOL4P4 and TAP4S). She’s especially interested in bringing formal methods closer to how developers actually write and reason about network code. \n\n\n🗓️ [Click here] to add event and zoom details to your calendar for September 24 at 8 am PT (virtual & free)
URL:https://p4.org/event/securing-p4-programs/
CATEGORIES:Events
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20261012
DTEND;VALUE=DATE:20261013
DTSTAMP:20260710T154838Z
CREATED:20260611T141804Z
LAST-MODIFIED:20260710T154838Z
UID:10000164-1791763200-1791849599@p4.org
SUMMARY:2026 P4 Workshop
DESCRIPTION:The P4 Workshop event is an opportunity for the P4 ecosystem to share knowledge\, insights and experiences across the broader community and to facilitate collaboration. This year the workshop will be a hybrid event and feature both in-person and pre-recorded content. The in-person portion will take place on October 12 in Silicon Valley (venue TBA). \nCall for Proposals is open and will close on August 1. \nFull event details
URL:https://p4.org/event/2026-p4-workshop/
CATEGORIES:Events
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20261207
DTEND;VALUE=DATE:20261211
DTSTAMP:20260722T141403Z
CREATED:20260716T154247Z
LAST-MODIFIED:20260722T141403Z
UID:10000167-1796601600-1796947199@p4.org
SUMMARY:EuroP4’26 (8th European P4 Workshop)
DESCRIPTION:The 8th edition of EuroP4 will be held between December 7-10\, 2026\, in co-location with CoNEXT’26 in Utrecht\, The Netherlands. The exact date will be announced soon. \nEuroP4’26 brings together networking researchers and practitioners to discuss cutting-edge\, P4-enabled research and P4-based technology. The workshop provides a venue for presenting and discussing research and projects related to P4\, as well as for more broadly discussing the needs of this research community. The workshop aims to forge new connections between researchers who already work with P4\, introduce more networking researchers to the P4 community\, and seed future top-tier publications\, innovation\, and contributions to this community. \nEvent website and CFP details
URL:https://p4.org/event/8th-european-p4-workshop-europ426/
CATEGORIES:Events
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