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DTSTART;TZID=UTC:20260319T080000
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CREATED:20251117T170038Z
LAST-MODIFIED:20260320T115620Z
UID:10000156-1773907200-1773910800@p4.org
SUMMARY:P4 Developer Days - SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate
DESCRIPTION:Register to attend this P4 Developer Days webinar\, “SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate”\nMarch 19 at 11 am ET/4 pm CET \nSlides (PDF) || Watch Recording \n\n\n\nAbstract\nMachine learning is increasingly used in programmable data planes\, such as switches and smartNICs\, to enable real-time traffic analysis and security monitoring at line rate. Decision trees (DTs) are particularly well-suited for these tasks due to their interpretability and compatibility with the Reconfigurable Match-Action Table (RMT) architecture. However\, current DT implementations require collecting all features upfront\, which limits scalability and accuracy due to constrained data plane resources. This paper introduces SpliDT\, a scalable framework that reimagines DT deployment as a partitioned inference problem over a sliding window of packets. \nBy dividing inference into sequential subtrees—each using its own set of top-k features—SpliDT supports more stateful features without exceeding hardware limits. An in-band control channel manages transitions between subtrees and reuses match keys and registers across partitions\, implemented using P4 for packet recirculation and control-plane coordination. This design allows physical resources to be shared efficiently while maintaining line-rate processing. To maximize accuracy and scalability\, SpliDT employs a custom training and design-space-exploration (DSE) workflow that jointly optimizes feature allocation\, tree depth\, and partitioning. Evaluations show that SpliDT supports up to 5x more features\, scales to millions of flows\, and outperforms baselines\, with low overhead and minimal time-to-detection (TTD). \n\n\nSpeaker\nMurayyiam Parvez is a Ph.D. candidate in the Department of Computer Science at Purdue University\, advised by Professor Muhammad Shahbaz and Professor Sonia Fahmy. Her research focuses on designing the next generation of hybrid software–hardware abstractions and architectures for emerging network security and machine learning applications\, with an emphasis on leveraging programmable switches to enable high-performance\, in-network intelligence. \n\nRegister to attend this webinar!
URL:https://p4.org/event/p4-developer-days-splidt-partitioned-decision-trees-for-scalable-stateful-inference-at-line-rate/
CATEGORIES:Events
ATTACH;FMTTYPE=image/png:https://p4.org/wp-content/uploads/sites/53/2025/11/Dev-Day-March-19.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Vancouver:20260304T080000
DTEND;TZID=America/Vancouver:20260304T090000
DTSTAMP:20260417T020016
CREATED:20251024T165254Z
LAST-MODIFIED:20260306T175333Z
UID:10000155-1772611200-1772614800@p4.org
SUMMARY:P4 Developer Days - P4Muse (P4 Modularity and Unification for Seamless Extensibility)
DESCRIPTION:Register to attend this P4 Developer Days webinar\, “P4Muse (P4 Modularity and Unification for Seamless Extensibility”\nDate: March 4\, 2026\nTime: 8:00am Pacific \nSlides (PDF) | Watch Recording \nAbstract\n\n\n\nDomain-specific programming languages such as P4 enable flexible and high-performance packet processing in programmable network data planes. However\, most P4 programs remain monolithic\, limiting the development of modular and reusable protocols and libraries. Introducing modularity to P4 has been challenging because existing approaches—such as trans-compilers and virtualization—operate outside the P4 language and compiler\, reducing backward compatibility and extensibility. P4Muse (P4 Modularity and Unification for Seamless Extensibility) addresses this challenge by introducing a compiler-managed approach to modularity within the P4C compiler. Without requiring any new syntax or annotations\, P4Muse introduces new compiler passes for automatic code merging\, enabling modular design\, reuse\, and seamless integration of complex network functionalities. Our results show that P4Muse effectively supports modular P4 program development without altering existing P4 syntax\, providing a robust solution that significantly improves code reusability\, flexibility\, and extensibility while maintaining backward compatibility. \n\n\n\n\nSpeakers\nMohsen Rahmati is a Ph.D. candidate in Computer Engineering at Polytechnique Montréal\, supervised by Professors Yvon Savaria\, François-Raymond Boyer\, and Jean-Pierre David. His research focuses on compiler design for programmable networks\, emphasizing modularity and reusability in the P4 language. He is the creator of P4Muse\, a compiler-managed modularity framework (accepted in IEEE Access\, 2025)\, and P4O2\, an object-oriented-inspired modularity in P4 currently under review at IEEE Access. \n\n  \nFrançois-Raymond Boyer received B.Sc. and Ph.D. degrees in computer science from Université de Montréal\, Montreal\, QC\, Canada\, in 1996 and 2001\, respectively. Since 2001\, he has been with Polytechnique Montréal\, Montréal\, where he is currently a Professor with the Department of Computer and Software Engineering. He has authored or co-authored more than 30 conference and journal papers. His current research interests include microelectronics\, performance optimization\, parallelizing compilers\, digital audio\, and body motion capture. He is a member of Regroupement Stratégique en Microélectronique du Québec\, Groupe de Recherche en Microélectronique et Microsystèmes\, and Observatoire Interdisciplinaire de Création et de Recherche en Musique.
URL:https://p4.org/event/p4-developer-days-p4muse-p4-modularity-and-unification-for-seamless-extensibility/
CATEGORIES:Events
ATTACH;FMTTYPE=image/png:https://p4.org/wp-content/uploads/sites/53/2025/10/Dev-Day-March-4.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20260204T080000
DTEND;TZID=UTC:20260204T090000
DTSTAMP:20260417T020016
CREATED:20251007T163320Z
LAST-MODIFIED:20260213T141052Z
UID:10000154-1770192000-1770195600@p4.org
SUMMARY:P4 Developer Days - Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA based SmartNICs
DESCRIPTION:In case you missed it\, you can now view the recording of this P4 Developer Days webinar\, “Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA-based SmartNICs”\n\n\n\nView Video\nView Slides\n\nAbstract\nThe exponential growth of cloud-native services\, 5G connectivity\, and data-intensive applications is driving unprecedented demand for high-throughput and flexible packet processing. Traditional fixed-function ASIC solutions\, while performant\, lack the adaptability to address emerging tunnelling protocols\, dynamic QoS enforcement\, and evolving custom workloads. P4\, an open and protocol-independent programming language for the data plane\, directly addresses these limitations by enabling developers to rapidly define and deploy advanced packet pipelines without RTL complexity. By combining FPGA Vendors P4 Compilers like Altera’s P4 Suite with iW-Fibre SmartNICs\, operators can synthesize programmable pipelines that sustain line-rate performance while remaining fully adaptable. \nDemonstration of the use cases – including checksum verification\, IP-in-IP tunnelling\, VXLAN encapsulation/decapsulation\, and standards-based QoS metering—illustrate how P4 empowers service providers and data centers to stay agile\, scalable\, and future-ready. \nSpeaker\nChethan T V is an Electronics an Communications Engineer possessing diverse experience in embedded industry as a digital design engineer with extensive expertise in FPGA design flow and SoC lifecycle. With strong project management skills\, he has led various challenging projects from conceptualization stage to execution and delivered successful products in the field of defense\, video\, military & commercial sectors. He is an Associate Director\, FPGA BU\, iWave Global – leading the Smart-NIC division from the ground up\, building a high-performing team\, and driving strategic projects in next-generation networking.
URL:https://p4.org/event/p4-developer-days-programmable-data-planes-for-the-cloud-era-harnessing-p4-on-fpga-based-smartnics/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20260121T080000
DTEND;TZID=UTC:20260121T080000
DTSTAMP:20260417T020016
CREATED:20250912T220334Z
LAST-MODIFIED:20260122T175551Z
UID:10000142-1768982400-1768982400@p4.org
SUMMARY:P4 Developer Days - In-Network Inference with P4: From Stateless to Hybrid Approaches
DESCRIPTION:P4 Developer Days webinar\, “In-Network Inference with P4: From Stateless to Hybrid Approaches” \nView Slides \nView Video \nAbstract\nIn-network machine learning (ML) techniques employ the P4 language to embed trained ML models directly into programmable network data planes. This has enabled novel applications in network security\, routing optimization\, and traffic classification\, amongst others. This presentation charts the evolution of these techniques\, starting with stateless\, packet-level inference models like Henna. It then explores the shift to stateful\, flow-level approaches as demonstrated in Flowrest. The talk culminates with Jewel\, a novel hybrid system that performs joint packet and flow-level inference for improved accuracy and efficiency. This journey from stateless to hybrid methodologies highlights the advancements and trade-offs in building intelligent\, high-performance\, and ML-empowered networks with P4.\n\n \nSpeaker\nAristide Akem is a Lecturer in Computer Science within the Cyberphysical Systems Group in the School of Electronics and Computer Science at the University of Southampton. Before joining Southampton\, he was a postdoctoral researcher in the Computing Infrastructure Group at the University of Oxford. His research spans machine learning\, network programming with P4\, and mobile networking\, with applications in network security\, IoT\, and energy. He earned his PhD from Universidad Carlos III de Madrid and IMDEA Networks Institute\, following a Master of Science in Electrical and Computer Engineering from Carnegie Mellon University Africa\, and a Master’s in Telecommunications Engineering from the University of Yaounde I.
URL:https://p4.org/event/p4-developer-days-in-network-inference-with-p4-from-stateless-to-hybrid-approaches/
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251210T080000
DTEND;TZID=UTC:20251210T080000
DTSTAMP:20260417T020016
CREATED:20250912T220323Z
LAST-MODIFIED:20251212T154953Z
UID:10000140-1765353600-1765353600@p4.org
SUMMARY:P4 Developer Days - Programmable Hardware Emulation Environment for Realistic and Scalable Network Testing
DESCRIPTION:P4 Developer Days: “Programmable Hardware Emulation Environment for Realistic and Scalable Network Testing” \nView Slides \nView Video \nAbstract\nNetwork emulators are essential for testing and validating new networking solutions before deployment. In this presentation\, we will showcase a hardware-based emulation framework that brings programmable switches and SmartNIC awareness to network experimentation. Our environment enables realistic and scalable evaluation of offloading\, host interaction\, and in-network processing. Through a simple API\, researchers can define and deploy multi-switch\, multi-host topologies; configure diverse link characteristics (e.g.\, bandwidth\, latency\, packet loss); and generate realistic traffic patterns. Finally\, we validate the environment using multiple state-of-the-art scenarios\, assessing robustness by reproducing and extending prior experiments across an expanded evaluation space. \nSpeakers\nFabricio Rodriguez received the M.Sc. and Ph.D. degrees in Electrical Engineering from the Universidade Estadual de Campinas in 2018 and 2024\, respectively. He was a researcher with the Information Networking Technologies Research Innovation Group (INTRIG)\, participating in projects with Ericsson\, Padtec\, and RNP. He is currently a Research Scientist at Telefónica Research\, Spain. His research interests include programmable networks\, in-network applications\, security\, and network performance. \n  \nFrancisco Vogt received the bachelor’s degree in computer science from the Federal University of Pampa and the master’s degree in computer engineering from the Universidade Estadual de Campinas\, Brazil\, where he is currently pursuing the Ph.D. degree in electrical engineering. He is currently a Visiting Researcher with the University of Amsterdam and works with the Multiscale Networked Systems (MNS) Research Group. He is involved as a Researcher with Ericsson on the project “SMARTNESS 2030: SMART NEtworks and ServiceS for 2030.” His research interests include programmable networks\, network monitoring\, network function offloading\, and network testing. \nRegister to attend this webinar! \n 
URL:https://p4.org/event/p4-developer-days-programmable-hardware-emulation-environment-for-realistic-and-scalable-network-testing/
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251203T080000
DTEND;TZID=UTC:20251203T080000
DTSTAMP:20260417T020016
CREATED:20250912T220324Z
LAST-MODIFIED:20251204T193414Z
UID:10000141-1764748800-1764748800@p4.org
SUMMARY:P4 Developer Days - QuIP: A P4 Quantum Internet Protocol Prototyping Framework
DESCRIPTION:P4 Developer Days webinar\, “QuIP: A P4 Quantum Internet Protocol Prototyping Framework” \nView Slides \nView Video \nAbstract\n\n\nQuantum entanglement is so fundamentally different from a network packet that several quantum network stacks have been proposed; one of which has even been experimentally demonstrated. Several simulators have also been developed to make up for limited hardware availability\, and which facilitate the design and evaluation of quantum network protocols. However\, the lack of shared tooling and community-agreed node architectures has resulted in protocol implementations that are tightly coupled to their simulators. Besides limiting their reusability between different simulators\, it also makes building upon prior results and simulations difficult. To address this problem\, we have developed QuIP: a P4-based Quantum Internet Protocol prototyping framework for quantum network protocol design. QuIP is a framework for designing and implementing quantum network protocols in a platform-agnostic fashion. It achieves this by providing the means to flexibly\, but rigorously\, define device architectures against which quantum network protocols can be implemented in the network programming language P416. QuIP also comes with the necessary tooling to enable their execution in existing quantum network simulators. We demonstrate its use by showcasing V1Quantum\, a completely new device architecture\, implementing a link- and network-layer protocol\, and simulating it in the existing simulator NetSquid. \nSpeaker\nWojciech Kozlowski is the Quantum Communication Topic Lead at SURF. He completed his MSci in Theoretical Quantum Physics at the University of Cambridge and his PhD in Atomic and Laser Physics at the University of Oxford. Since then\, Wojciech has been involved with networks\, both classical and quantum. After his PhD he joined Metaswitch in London where he worked as a software engineer developing (classical) control planes. In 2019\, Wojciech moved to the Netherlands where he worked  as a postdoc and later quantum network engineer at the TU Delft before joining SURF in 2024.
URL:https://p4.org/event/p4-developer-days-quip-a-p4-quantum-internet-protocol-prototyping-framework/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251119T080000
DTEND;TZID=UTC:20251119T080000
DTSTAMP:20260417T020016
CREATED:20250912T220322Z
LAST-MODIFIED:20251202T154731Z
UID:10000137-1763539200-1763539200@p4.org
SUMMARY:P4 Developer Days - Implementation of Periodic Behavior with P4: Challenges and Solutions on Intel Tofino with Application in Time-Sensitive Networking (TSN)
DESCRIPTION:P4 Developer Days webinar\, “Implementation of Periodic Behavior with P4: Challenges and Solutions on Intel Tofino with Application in Time-Sensitive Networking (TSN)” \nView Slides \nView Video \nAbstract\nImplementing periodic time behavior in hardware data planes is challenging due to limited arithmetic capabilities such as the lack of modulo operations\, restricted timestamp precision\, and resource constraints. This talk presents a general mechanism for implementing periodic time logic in P4\, i.e.\, enabling data plane behavior that repeats in fixed time intervals\, applicable to a broad range of time-aware applications. The mechanism enables periodic packet matching by mapping absolute timestamps to relative positions within a hyperperiod. To emulate hyperperiod boundaries\, we leverage the switch’s internal packet generator to generate periodic trigger packets that act as time anchors for computing relative timestamps. \n\nAs a concrete use case\, we apply this mechanism to implement Per-Stream Filtering and Policing (PSFP) as defined in IEEE 802.1Qci. Our implementation on Intel Tofino™ hardware demonstrates reliable time-based gating at line rate. Finally\, we discuss how this periodicity mechanism can be extended to implement additional time-sensitive features such as the Time-Aware Shaper (TAS)\, offering a scalable foundation for deterministic network behavior in P4-based systems.\n\n\nSpeaker\nFabian Ihle received his bachelor’s (2021) and master’s degrees (2023) in computer science at the University of Tuebingen. Afterwards\, he joined the communication networks research group of Prof. Dr. Habil Michael Menth as a Ph.D. student. His research interests include software-defined networking\, P4-based data plane programming\, resilience\, and Time-Sensitive Networking (TSN). \n\n 
URL:https://p4.org/event/p4-developer-days-implementation-of-periodic-behavior-with-p4-challenges-and-solutions-on-intel-tofino-with-application-in-time-sensitive-networking-tsn/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251112T080000
DTEND;TZID=UTC:20251112T080000
DTSTAMP:20260417T020016
CREATED:20250912T220317Z
LAST-MODIFIED:20251119T163005Z
UID:10000134-1762934400-1762934400@p4.org
SUMMARY:P4 Developer Days - AR/CG Network Traffic Classification in Programmable Dataplane
DESCRIPTION:P4 Developer Days webinar\, “AR/CG Network Traffic Classification in Programmable Dataplane”\nDate: November 12\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nIn this presentation\, we explore the importance of classifying AR/CG traffic directly within the network device to enable low-latency\, intelligent forwarding. We outline the end-to-end process of feature extraction and deployment within a programmable data plane\, focusing on how key traffic features are computed and mirrored in P4-enabled switches. We also discuss the training of machine learning models tailored for the P4 data plane and their use in online pattern matching. Finally\, we introduce our key contributions\, including the extracted features\, developed codebase\, and publicly available repositories. \nSpeaker\nAlireza Shirmarz received his B.Sc. in Computer Engineering from Shahed University in 2009 and his M.Sc. in Network Engineering from Amirkabir University of Technology (Tehran Polytechnic) in 2014. He earned his Ph.D. in Computer Engineering from IAU-Tehran North Branch in 2020. Since 2014\, he has been actively teaching undergraduate courses in computer science and engineering and has been involved in graduate and Ph.D. supervision since 2020. \nHis research focuses on the intersection of networking and AI/ML\, particularly in optimizing Quality of Experience (QoE) for real-time and interactive applications in future networks\, including 6G. He specializes in intelligent data plane solutions\, SDN architectures\, and QoS/QoE management. Currently\, he is a Postdoctoral Researcher at UFSCar\, advancing AI/ML applications in networking. \n 
URL:https://p4.org/event/p4-developer-days-ar-cg-network-traffic-classification-in-programmable-dataplane/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251029T080000
DTEND;TZID=UTC:20251029T080000
DTSTAMP:20260417T020016
CREATED:20250912T220317Z
LAST-MODIFIED:20251104T173524Z
UID:10000135-1761724800-1761724800@p4.org
SUMMARY:P4 Developer Days - P4sim: Protocol-Independent Packet Processors in ns-3
DESCRIPTION:P4 Developer Days webinar\, “P4sim: Protocol-Independent Packet Processors in ns-3”\nDate: October 29\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nNetwork simulation plays a crucial role in evaluating new architectures\, protocols\, and algorithms before deployment. While ns-3 is one of the most widely used discrete-event network simulators\, it lacks native support for programmable data plane behaviors described in P4. P4sim addresses this gap by integrating P4’s protocol-independent\, table-driven packet processing model into the ns-3 simulation framework. This talk introduces the architecture and capabilities of P4sim\, demonstrates how developers can prototype and test P4 programs in simulation environments\, and presents example use cases such as custom switching logic and in-band telemetry. Attendees will learn about the architecture and design of P4sim\, which supports P4 architectures like V1Model\, PSA\, and PNA. The talk highlights its integration with ns-3 and showcases practical use cases. P4sim enables early development and testing of P4 programs without hardware\, making it ideal for researchers and developers in programmable networking and simulation. \nSpeaker\n \nMingyu Ma is a Ph.D. researcher at Technische Universität Dresden\, Germany\, focusing on computer networks\, programmable data planes\, and simulation platforms. Mingyu has been actively involved in bridging the gap between research prototypes and real-world deployments\, with hands-on experience in P4\, ns-3 and traffic control. He regularly contributes to academic conferences and open-source communities related to network systems and simulation. \n  \n\n 
URL:https://p4.org/event/p4-developer-days-p4sim-protocol-independent-packet-processors-in-ns-3/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251013T120000
DTEND;TZID=UTC:20251013T153000
DTSTAMP:20260417T020016
CREATED:20250912T220305Z
LAST-MODIFIED:20251119T000559Z
UID:10000131-1760356800-1760369400@p4.org
SUMMARY:2025 P4 Workshop
DESCRIPTION:October 13th\, Noon – 3:30pm (in-person) – San Jose Convention Center\, Lower Level\, Room LL21B \nThe P4 Workshop event is an opportunity for the P4 ecosystem to share knowledge\, insights and experiences across the broader community and to facilitate collaboration. This year the workshop will be a hybrid event and feature both in-person and pre-recorded content. The in-person portion of the workshop will take place on October 13th in conjunction with the 2025 OCP Global Summit at the San Jose Convention Center in San Jose\, California. \nIn addition\, a P4 booth will be in the OCP Global Summit exhibit hall – make sure and stop by to talk with community members and learn about P4\, how its used and how to participate. Don’t miss a demo – “Gigaflow: Pipeline-Aware Caching in Virtual Switches with P4”. \nP4 Workshop Agenda (October 13th – noon – 3:30pm)\n\nWelcome – Fernando Ramos\nGeneral Chair 2025 P4 Workshop\nView Video | View Slides\nKEYNOTE: Mina Tahmasbi Arashloo – “High-Level and Target-Agnostic Transport Programs”\nAssistant Professor Canada Research Chair in Minimizing Human Error in Modern Networks Cheriton School of Computer Science\, University of Waterloo\nAbstract: Over the past two decades\, programming abstractios for packet processing have gained widespread adoption. These abstractions enable network operators to specify packet processing logic in high-level\, domain-specific languages that are independent of the underlying hardware architecture of packet processing nodes. This approach has unlocked numerous benefits\, including compiler-driven generation of efficient low-level implementations\, portability across diverse execution environments\, and automated testing and verification. Most existing abstractions\, however\, primarily focus on L2/L3 packet processing. In this talk\, we highlight the need for new programming abstractions that capture the complexities of network mechanisms essential for quality of service\, specifically transport protocols.\nView Video | View Slides\nVictor Rios – “DVaaS Detective: The Case of the Failing Tests”\nSoftware Engineer\, Google\nView Video | View Slides\nAnand Sridharan – “Cisco Silicon One: Unifying Network Forwarding with P4 Programmability”\nDistinguished Engineer\, Cisco\nView Video | View Slides\nBREAK\nTom Herbert – “Unifying P4 with eBPF and DPDK via XDP2”\nCEO\, XDPnet\nView Video | View Slides\nDebashis Chatterjee – “New Dawn of P4”\nSenior Director of Engineering\, Intel\nView Video | View Slides\nFabian Ruffy | Vladimir Gurevich – “XASM: A Foundation to Program the X2 with P4”\nSoftware Architect | Customer Solutions Architect\, XSight Labs\nView Video | View Slides\nKEYNOTE: Krishna Doddapaneni – “Using P4 NICs for Resilient Scale-out GPU Interconnect”\nCorporate Vice President\, AMD Pensando\nAbstract: AI transports demand hardware-based solution for low latency\, high throughput GPU interconnects. P4 seems a perfect match for demanding datapath transport enabled on programmable NIC for scale-out Ethernet fabrics. The industry is standardizing packet processing\, memory transfers\, message processing\, reliability\, multipathing\, etc. over the last few years. And we are at the beginning of building and standardizing these solutions. As network components multiplies — from cables and NICs to switches and transceivers\, failures become an inevitability. Chasing a myth of perfect reliability\, a more practical approach is to design a programmable network that anticipates and handles these failures gracefully. \n\nThis talk discusses how AMD leverages the P4 to build a robust solution that overcomes network failures\, implementing a multi-plane architecture and advanced failure-handling mechanisms. How P4 capabilities demonstrate network data plane programmability is a foundational requirement in today’s demanding and unforgiving AI environments.\nView Video | View Slides\n\nAndy Fingerhut – P4 Workshop Wrap-up\nPrincipal Engineer\, Cisco\n\nP4 Workshop Pre-Recorded Talks\n\nEric Campbell – “When P4 Isn’t Enough: Specifying The Control Interface”\nPostdoctoral Research Fellow\, UT Austin\nView Video | View Slides\nMehmet Emin Sahin – “High-Accuracy Updatable Bloom Filters for Robust Network Security in Programmable Networks”\nSystems and Network Administrator\, The Scientific and Technological Research Council of Turkiye\nView Video | View Slides\nMirek Walukiewicz – “Virtual IP Load Balancer using P4”\nPrincipal Engineer\, Altera\nView Video | View Slides\nPhani Suresh Paladugu – “Enabling Programmable Performance: Memory and Interconnect Innovation for AI-Centric Data Planes”\nExecutive Director – Product Management\, Synopsys\nView Video | View Slides\nJitesh Sreedharan Nambiar – “AI‑Enabled BOM Lifecycle for P4‑Programmable Infrastructure Reliability”\nBE Graduate\, Mumbai University\nView Video | View Slides\nMohammad Firas Sada – “Cross-Federated P4 Research Testbed for Wide-Area Programmable Networking Experiments”\nData Science Research Specialist\, San Diego Supercomputer Center\nView Video | View Slides\nShaan Nagy | Ali Kheradmand – “Automated Switch Validation with Path-Complete Testing at Scale”\nPhD Student\, UCSD | Senior Software Engineer\, Google\nView Video | View Slides\nAmith Gspn – “Real-Time Encrypted Traffic Classification with P4 and DPDK”\nGraduate Student Assistant and PhD Student\, University of South Carolina\nView Video | View Slides\n\nP4 Demo\nAdvay Singh | Ali Imran | Muhammad Shahbaz – “Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern SmartNICs”\nResearch Assistant | Graduate Student Research Assistant |  Assistant Professor EECS – Computer Science and Engineering\, University of Michigan\nView Demo \nGeneral Chair\nFernando Ramos\, University of Lisbon \nProgram Committee\nAmedeo Sapio\, NVIDIA\nAndy Fingerhut\, Cisco\nBen Pfaff\, Feldera\nChris Sommers\, KeySight\nGianni Antichi\, Politecnico di Milano & Queen Mary University of London\nJonathan DiLorenzo\, Google\nMario Baldi\, NVIDIA\nMuhammad Shahbaz\, University of Michigan\nVladimir Gurevich\, P4ica \nAll attendees and participants are expected to behave in accordance with professional standards and the Linux Foundation Events Code of Conduct – for more information\, see the full Code here.
URL:https://p4.org/event/2025-p4-workshop/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251001T090000
DTEND;TZID=UTC:20251001T090000
DTSTAMP:20260417T020016
CREATED:20250912T220316Z
LAST-MODIFIED:20251007T204714Z
UID:10000133-1759309200-1759309200@p4.org
SUMMARY:P4 Developer Days - Enabling Portable and High-Performance SmartNIC Programs with Alkali
DESCRIPTION:Date: October 1\, 2025\nTime: 9:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nProgramming SmartNICs today is notoriously difficult. NICs from different vendors—or even different generations of the same vendor—exhibit significant variation in hardware parallelism\, memory hierarchies\, and interconnects. As a result\, porting programs across NICs is labor-intensive and requires extensive manual refactoring to meet performance expectations on each target. \nIn this presentation\, we will present the demo and design of Alkali\, a SmartNIC compilation framework that enables developers to write target-independent programs\, while the compiler automatically handles cross-NIC porting and performance tuning. Alkali achieves this by: (1) introducing a novel intermediate representation (IR) that supports building a reusable and extensible compiler across diverse NICs\, and (2) developing an optimization algorithm that automatically transforms and parallelizes programs based on the target NIC’s hardware characteristics. \nAlkali is built on the MLIR infrastructure and is fully open source (https://github.com/utnslab/Alkali). It currently supports four distinct NIC backends and continues to grow\, including future support for P4 as part of an effort to make SmartNIC programming more portable and productive. \nSpeakers\nJiaxin Lin is an incoming assistant professor at Cornell University. She received her Ph.D. from UT Austin in the summer of 2025. Her research aims to design innovative software and hardware for accelerated data center networks. She has received the Google and Meta PhD Fellowships in Computer Networking and was selected as an MIT EECS Rising Star in 2024. \n  \n \nZhiyuan Guo is a final-year PhD student at UC San Diego. His research focuses on co-designing datacenter systems and applications for resource disaggregation. He is actively extending the concept of disaggregation and cohesive design to various datacenter systems\, including remote memory\, networking accelerators\, and machine learning infrastructure. \n  \n 
URL:https://p4.org/event/p4-developer-days-enabling-portable-and-high-performance-smartnic-programs-with-alkali/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250925T080000
DTEND;TZID=UTC:20250925T080000
DTSTAMP:20260417T020016
CREATED:20250912T220305Z
LAST-MODIFIED:20250930T162043Z
UID:10000130-1758787200-1758787200@p4.org
SUMMARY:P4 Developer Days - From Semantics to Software: Building a Verification Ecosystem for P4 using HOL4P4
DESCRIPTION:P4 Developer Days webinar\, “From Semantics to Software: Building a Verification Ecosystem for P4 using HOL4P4”\nDate: September 25\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO\nVIEW SLIDES \nAbstract\nWe present a comprehensive formal verification ecosystem for the P4 network programming language\, built upon HOL4P4\, an abstract model of P4 execution embedded in the interactive theorem prover HOL4. The HOL4P4 formalization provides a semantics and a corresponding type system with formally verified progress\, preservation\, and type-soundness theorems. In addition\, it has been validated using a test suite from the P4 reference implementation. \nFrom this robust semantic foundation\, we have developed multiple practical verification tools. Our proof-producing symbolic execution engine enables functional correctness verification of entire real-world P4 programs\, with all results mechanically verified against the HOL4P4 semantics. Additionally\, we present a formally verified P4 software switch that maintains correctness guarantees from source to binary by leveraging both HOL4P4 and the verified CakeML compiler. This switch integrates seamlessly with existing network testing frameworks like Mininet while demonstrating decent performance compared to existing similar solutions.\n \nTogether\, these contributions demonstrate how rigorous formalization can serve as the foundation for a complete ecosystem of verification tools\, bridging the gap between theoretical guarantees and practical network development while meeting the growing demand for formal assurances in critical network infrastructure. \nSpeaker\nDidrik Lundberg combines academic research as a PhD candidate at KTH Royal Institute of Technology with practical engineering experience at Saab AB. He specializes in interactive theorem proving and formal verification\, particularly for low-level and network-related systems. His current focus is developing tools based on the HOL4P4 formalization of P4. \n 
URL:https://p4.org/event/p4-developer-days-from-semantics-to-software-building-a-verification-ecosystem-for-p4-using-hol4p4/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250917T080000
DTEND;TZID=UTC:20250917T080000
DTSTAMP:20260417T020016
CREATED:20250912T220322Z
LAST-MODIFIED:20250919T175701Z
UID:10000138-1758096000-1758096000@p4.org
SUMMARY:2025 P4 GSoC Wrap-up
DESCRIPTION:Date: September 17\, 2025\nTime: 8:00am Pacific \nThe wrap-up session highlights results of the projects hosted by The P4 Language Consortium during Google Summer of Code (GSoC) 2025. In its second consecutive year of participation\, we are pleased to share the results from each of the projects. During this session\, contributors will present their work\, share key outcomes\, and participate in a live Q&A. \nOfficial GSoC 2025 Profile: The P4 Language Consortium \nVIEW VIDEO \nAgenda \n\nOpening – Bili Dong\, Google \nP4 GSoC project presentation + discussion:\n\nBMv2 with All Possible Output Packets – Xiyu Hao\, New York University\nP4Sim Control Plane Enhancement – Vineet Goel\, Indian Institure of Technology Roorkee\nAccelerating OVS with Gigaflow: A Smart Cache for SmartNICs – Advay Singh\, University of Michigan\nSpliDT: Scaling Stateful Decision Tree Algorithms in P4 – Sankalp Jha\, Ajay Kumar Garg Engineering College\n\n\n\n  \n 
URL:https://p4.org/event/2025-p4-gsoc-wrap-up/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250910T160000
DTEND;TZID=UTC:20250910T160000
DTSTAMP:20260417T020016
CREATED:20250912T220323Z
LAST-MODIFIED:20250919T172457Z
UID:10000150-1757520000-1757520000@p4.org
SUMMARY:P4 Developer Days - Mechanizing the P4 Language Specification with P4-SpecTec
DESCRIPTION:Date:  September 10th 4:00pm PST | September 11th – 8:00am KST \nVIEW VIDEO\nVIEW SLIDES \nAbstract\nThe P4 language has four main representations of its syntax and semantics: the official specification\, formalizations\, implementations\, and a test suite. While the four representations are intended to consistently define the P4 language\, they often diverge\, as each is managed by different parties and evolves at a different pace. This lack of alignment complicates both specification evolution and compiler maintenance. \n\n\nTo address this challenge\, we present P4-SpecTec\, a mechanized specification infrastructure for the P4 language. Inspired by successful language mechanization frameworks such as Wasm-SpecTec for WebAssembly and ESMeta for JavaScript\, P4-SpecTec introduces a formal\, complete\, and mechanized P4 language definition. From this single source of truth — the mechanized specification — we aim to generate multiple backends\, such as a type checker\, interpreter\, test suite\, and specification document\, in a consistent and automated manner. \nP4-SpecTec is an ongoing project\, where we currently mechanized the P4 type system. Notably\, our mechanized type system is executable. That is\, the typing rules can be executed\, acting as a P4 type checker. Our mechanized specification passes more than 97% of the applicable tests in the p4c test suite. This process already revealed inconsistencies and underspecified behaviors in both the P4 specification and its reference compiler. Based on the mechanized model\, we further developed a negative test generation technique that automatically produces ill-typed P4 programs that trigger subtle and diverse ill-typed conditions in the P4 type system. This approach has uncovered 11 compiler bugs and 12 soundness issues in the p4c frontend. \nThis talk introduces the design of P4-SpecTec\, current progress\, and long-term vision for a more robust and consistent P4 language ecosystem. \nSpeaker\nJaehyun Lee is a graduate student in the Programming Language Research Group at KAIST\, advised by Sukyoung Ryu. His research focuses on mechanizing programming language definitions to improve their reliability and precision. He leads the P4-SpecTec project\, which is a mechanized specification infrastructure for P4. Previously\, he contributed to the Wasm-SpecTec project\, now part of the official WebAssembly specification authoring toolchain. As part of that effort\, he co-authored the paper “Bringing the WebAssembly Standard Up to Speed with SpecTec”\, presented at PLDI 2024. His goal is to make language specifications reliable and better aligned with the needs of the developer community.
URL:https://p4.org/event/p4-developer-days-mechanizing-the-p4-language-specification-with-p4-spectec/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250820T090000
DTEND;TZID=UTC:20250820T090000
DTSTAMP:20260417T020016
CREATED:20250912T220316Z
LAST-MODIFIED:20250915T184729Z
UID:10000132-1755680400-1755680400@p4.org
SUMMARY:P4 Developer Days - Detecting Stragglers in Programmable Data Plane
DESCRIPTION:Date: August 20\, 2025Time 9:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nFlow scheduling mechanisms in modern datacenters aim to reduce flow completion time (FCT). However\, scheduling mechanisms that operate without prior knowledge\, such as PIAS\, or with imprecise flow information like QClimb\, can inadvertently introduce stragglers–packets within a flow that experience significantly higher queueing delays than others. These stragglers can lead to prolonged FCT\, undermining the goals of flow scheduling. In this talk\, we present StragFlow\, a data-plane tool for straggler detection. We implemented StragFlow in P4 using 740 lines of code. We evaluated StragFlow using real-world network traces and demonstrate that it can effectively detect stragglers across different scheduling schemes and various link conditions. Our results show that StragFlow can provide valuable insights into straggler distribution\, helping operators diagnose and mitigate flow scheduling issues to improve overall network performance. \nSpeaker\nRiz Maulana is a PhD Candidate within IRIS Cluster in the Department of Mathematics and Computer Science at Eindhoven University of Technology\, The Netherlands. His research interest includes programmable data plane\, probabilistic data structures\, and network monitoring. \n 
URL:https://p4.org/event/p4-developer-days-detecting-stragglers-in-programmable-data-plane/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250806T080000
DTEND;TZID=UTC:20250806T080000
DTSTAMP:20260417T020016
CREATED:20250912T220305Z
LAST-MODIFIED:20250915T225142Z
UID:10000129-1754467200-1754467200@p4.org
SUMMARY:P4 Developer Days - Gateway Use Case Architecture for Network Applications
DESCRIPTION:Date: August 6\, 2025Time: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES\nAbstract \nNetwork applications demand ever-increasing performance and flexibility. Mapping P4 programs directly to FPGA hardware offers a powerful solution\, but the design process can be complex. This presentation demonstrates a new toolchain for efficiently mapping P4 programs to Altera FPGAs\, significantly accelerating gateway applications. Presentation leads attendees through the complete flow\, from high-level P4 specification down to a fully synthesized FPGA design using a practical gateway example. Attendees will learn how this toolchain leverages p4 language capabilities to map the user application into FPGA. This session is ideal for network architects and hardware engineers seeking to leverage the power of P4 and FPGA acceleration for next-generation network applications. \nSpeaker\nPavel Benacek is Technical Lead at Altera with more than 12 years of experience in networking technology from research and industry. He is mainly working on hardware/software co-designs and high-level synthesis topics. He holds the Ph.D. at the Czech Technical University in Prague where he was working on theory of P4 language mapping to RTL design that can be synthesized to FPGA. \n 
URL:https://p4.org/event/p4-developer-days-gateway-use-case-architecture-for-network-applications/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250709T080000
DTEND;TZID=UTC:20250709T080000
DTSTAMP:20260417T020016
CREATED:20250912T220304Z
LAST-MODIFIED:20250915T225148Z
UID:10000128-1752048000-1752048000@p4.org
SUMMARY:P4 Developer Days - P4-based AI Feature Extractor for Volumetric Firewall Use Cases
DESCRIPTION:Date: July 9\, 2025Time 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract \nUsing volumetry data is a very important feature of many firewalls from major security vendors. The changing security landscape and a need for performance and flexibility drive the use of AI/ML engines working more efficiently. The presentation shows an example of the use of P4 language to prepare a training feature and an example of an inference engine using P4 as a feature extractor for the SYN-FLOOD attack detector. The P4\, as a packet processing language\, can be used to define the network traffic-based features for AI/ML processing. The AI/ML engines can be abstracted as P4 externs. The P4 defines what packet fields are of interest in AI/ML process. Such P4 engine implementation (based on hardware or software) can also prepare/preprocess the AI/ML engine input (for example\, rate of some packets or counter selection). It can also prepare the packet-based response using AI/ML external outcome. The presentation provides an overview of some challenges\, like a lack of standardized datasets and performance requirements. \nSpeaker\nMirek Walukiewicz is a Principal Engineer at Altera with more than 32 years of experience in networking technology. He is a Solution Architect actively working with customers on various P4 applications using FPGA-like security\, packet scheduling\, clock synchronization\, and more. He drives P4 efforts inside Altera. \n 
URL:https://p4.org/event/p4-developer-days-p4-based-ai-feature-extractor-for-volumetric-firewall-use-cases/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250611T080000
DTEND;TZID=UTC:20250611T080000
DTSTAMP:20260417T020016
CREATED:20250912T220304Z
LAST-MODIFIED:20250915T225203Z
UID:10000127-1749628800-1749628800@p4.org
SUMMARY:P4 GSoC 2025 Kickoff Meeting
DESCRIPTION:Learn about the projects hosted by the P4 Project in Google Summer of Code (GSoC) 2025. Each project will be presented by the contributor. \nAgenda \n\n\n\nIntroduction – Nate Foster\nGSoC proposal presentation + discussion:\n\n\n\n\n\n\n\n\nBMv2 With All Possible Output Packets – Xiyu Hao\nP4Sim Control Plane Enhancement – Vineet Goel\nP4MLIR: MLIR-based high-level IR for P4 compilers – Xiaomin Liu\nAccelerating OVS with Gigaflow: A Smart Cache for SmartNICs – Advay Singh\nSpliDT: Scaling Stateful Decision Tree Algorithms in P4 – Sankalp Jha\n\n\n\n\n\nVIEW VIDEO \nVIEW SLIDES
URL:https://p4.org/event/p4-gsoc-2025-kickoff-meeting/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250604T080000
DTEND;TZID=UTC:20250604T080000
DTSTAMP:20260417T020016
CREATED:20250912T220259Z
LAST-MODIFIED:20250915T225237Z
UID:10000126-1749024000-1749024000@p4.org
SUMMARY:P4 Developer Days - Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern Smart NICs
DESCRIPTION:P4 Developer Days webinar\, “Pipeline-Aware Sub-Traversal Caching for Modern Smart NICs”\nDate: June 4\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nThe success of modern public/edge clouds hinges heavily on the performance of their end-host network stacks if they are to support the emerging and diverse tenants’ workloads (e.g.\, distributed training in the cloud to fast inference at the edge). Virtual Switches (vSwitches) are vital components of this stack\, providing a unified interface to enforce high-level policies on incoming packets and route them to physical interfaces\, containers\, or virtual machines. As performance demands escalate\, there has been a shift toward offloading vSwitch processing to SmartNICs to alleviate CPU load and improve efficiency. However\, existing solutions struggle to handle the growing flow rule space within the NIC\, leading to high miss rates and poor scalability. In this paper\, we introduce Gigaflow\, a novel caching system tailored for deployment on SmartNICs to accelerate vSwitch packet processing. Our core insight is that by harnessing the inherent pipeline-aware locality within programmable vSwitch pipelines—defining policies (e.g.\, L2\, L3\, and ACL) and their execution order (e.g.\, using P4 and OpenFlow)—we can create cache rules for shared segments (sub-traversals) within the pipeline\, rather than caching entire flows. These shared segments can be reused across multiple flows\, resulting in higher cache efficiency and greater rule-space coverage. Our evaluations—performed using Xilinx Alveo U250 data center accelerator running a Gigaflow pipeline written in P4—show that Gigaflow achieves up to a 51% improvement in cache hit rate (average 25% improvement) over traditional caching solutions (i.e.\, Megaflow)\, while capturing up to 450x more rule space within the limited memory of today’s SmartNICs—all while operating at line speed.  \nPublication Link : https://dl.acm.org/doi/10.1145/3676641.3716000 \nSpeaker\nAnnus Zulfiqar is a PhD candidate at the University of Michigan with Professor Muhammad Shahbaz. His research focuses on designing next generation hardware/software abstractions and architectures for emerging data center networking applications. Currently\, he is working on designing a scalable and efficient fast path for the Open vSwitch\, which is a widely used software switch in modern data centers. He is also working on ML for Systems where he has contributed to automatic generation of optimized data plane ML models and the development of scalable decision trees for programmable switches. \n 
URL:https://p4.org/event/p4-developer-days-gigaflow-pipeline-aware-sub-traversal-caching-for-modern-smart-nics/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250529T080000
DTEND;TZID=UTC:20250529T080000
DTSTAMP:20260417T020016
CREATED:20250912T220259Z
LAST-MODIFIED:20250915T225242Z
UID:10000125-1748505600-1748505600@p4.org
SUMMARY:P4 Developer Days - P4 on Silicom ThunderFjord SmartNIC
DESCRIPTION:P4 Developer Days webinar\, “P4 on Silicom ThunderFjord SmartNIC”\nDate: May 29\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nThe integration of P4 into the FPGA of the Silicom ThunderFjord SmartNIC brings unprecedented flexibility and programmability to modern networking. This presentation explores the capabilities of the ThunderFjord SmartNIC\, highlighting how P4 enables dynamic packet processing directly on the hardware. We will delve into the architecture of the SmartNIC\, its role in enhancing network performance\, and the benefits of using P4 to implement custom protocols\, traffic management\, and network offload functions. \nSpeakers \nLars Munch \, Senior Software Engineer\, Silicom Denmark \nLars holds a Master’s degree in Computer Science from the Technical University of Denmark (DTU)\, with research experience in embedded systems. With over two decades of expertise\, he has developed high-performance software solutions for SmartNICs\, IoT devices\, and embedded Linux platforms. Currently\, Lars is a Senior Software Engineer at Silicom Denmark\, where he is responsible for the design\, development\, and optimization of software solutions related to SmartNICs\, playing a key role in delivering advanced networking technologies. \nEleftherios Kyriakakis\, FPGA Developer\, Silicom Denmark \nEleftherios holds a PhD from the Technical University of Denmark (DTU) with a research focus on “Time-predictable End-system Design for Real-Time Communication”.  He specializes in FPGA and ASIC design\, particularly in developing fault-tolerant and real-time systems. His most notable published works include the implementation of a fault-tolerant inter-chip Network-on-Chip (NoC) communication bridge on FPGAs\, memory controllers with single-event upset (SEU) detection\, and research on precise time protocol (PTP) and time-triggered networks. Currently\, Eleftherios is working as an FPGA engineer at Silicom Denmark\, where he is responsible for the design and development of proof-of-concept solutions for SmartNICs. \n 
URL:https://p4.org/event/p4-developer-days-p4-on-silicom-thunderfjord-smartnic/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250506T080000
DTEND;TZID=UTC:20250506T080000
DTSTAMP:20260417T020016
CREATED:20250912T220259Z
LAST-MODIFIED:20250915T225249Z
UID:10000124-1746518400-1746518400@p4.org
SUMMARY:P4 Developer Days - P4 in SDN-based Attack Detection and AI-driven Security Mechanisms
DESCRIPTION:May 6\, 2025 | 8:00am Pacific\nView Video \nView Slides \nAbstract\nSoftware-Defined Networking (SDN) is a promising network architecture that offers greater flexibility and scalability compared to traditional network infrastructures. This flexibility arises from the separation of the data plane from the control plane\, which enables the use of general-purpose devices\, commonly referred to as “dumb devices” in SDN. While this separation enhances network management and administration\, it also imposes processing limitations\, leading to increased overhead on the controller. This is precisely where P4\, a domain-specific programming language for packet processing\, becomes highly beneficial. \nIn the field of network security\, particularly in attack detection\, researchers have proposed various innovative methods. P4 can play a crucial role in advancing these solutions by leveraging a programmable data plane to offload processing tasks from the controller\, thereby achieving a more balanced distribution of computational load between the data and control planes. One of the most critical areas of application in this regard is the detection and mitigation of Distributed Denial-of-Service (DDoS) attacks. \nAdditionally\, there has been a significant rise in AI-based security solutions\, with machine learning (ML) being a prominent subfield. ML enables the development of custom AI agents tailored for specific tasks\, requiring the extraction of relevant features for training purposes. However\, without a programmable data plane\, this approach is impractical in both SDN and traditional networks. With P4\, however\, such implementations become feasible\, opening new possibilities for AI-driven network security solutions. \nIn this webinar\, we will explore the use cases of P4 in SDN-based attack detection and AI-driven security mechanisms\, highlighting its potential to enhance modern network security strategies. \nSpeaker \nReza Fallahi Kapourchali holds an M.Sc. in Computer Networks from Bu-Ali Sina University\, Hamedan\, Iran. His research interests encompass a broad spectrum of critical areas\, including computer network security\, P4 technology\, wireless networks\, 5G networks\, the Industrial Internet of Things (IIoT)\, and network Quality of Service (QoS). His commitment to advancing innovation and knowledge in these fields is evidenced by his published articles\, which contribute to the development of secure and efficient network architectures.
URL:https://p4.org/event/p4-developer-days-p4-in-sdn-based-attack-detection-and-ai-driven-security-mechanisms/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20241028T080000
DTEND;TZID=UTC:20241028T080000
DTSTAMP:20260417T020016
CREATED:20250912T215845Z
LAST-MODIFIED:20250915T225259Z
UID:10000079-1730102400-1730102400@p4.org
SUMMARY:7th European P4 Workshop (EuroP4’24)
DESCRIPTION:Sponsored by AMD \n \n  \nThe 7th edition of EuroP4 was held on October 28th in conjunction with the 32nd IEEE International Conference on Network Protocols (ICNP 2024)\, in Charleroi\, Belgium. \nEuroP4’24 brings together networking researchers and practitioners to discuss cutting-edge\, P4-enabled research and P4-based technology. The workshop provides a venue for presenting and discussing research and projects related to P4\, as well as for more broadly discussing the needs of this research community. The workshop aims to forge new connections between researchers who already work with P4\, introduce more networking researchers to the P4 community\, and seed future top-tier publications\, innovation and contributions to this community. \nKeynotes\nShir Landau Feibish\, Senior Lecturer (Assistant Professor)\nDepartment of Mathematics and Computer Science\, Open University of Israel\nShir is a Senior Lecturer (Assistant Professor) and head of the RUNS lab at The Open University of Israel. Before joining The Open University\, Shir was a postdoctoral researcher at Princeton University. \nShir’s main interests are network telemetry and programmable networks. Her work focuses on building tools for network monitoring by tailoring streaming methods and compact data structures to the computational model and constraints of programmable devices. Shir has received several awards including the Eric and Wendy Schmidt Postdoctoral Award for Women in Mathematical and Computing Sciences and was named one of the Rising Stars in Networking and Communications of 2020 by the N2Women Organization. \n“Time-Aware Network Telemetry in the Data Plane” \nAbstract: Collecting network telemetry is essential for detecting problems in the network. In recent years we have seen an abundance of research on network telemetry in the data plane. Many of these solutions analyze traffic continuously over a long period of time\, while resetting the structure from time to time. If shorter time intervals are needed\, sliding windows are usually used\, yet these incur significant resource and management overhead. However\, often in order to understand what is happening in the network we need to measure events that have recently happened.  \nWe explore the concept of time-aware network telemetry and propose several different paradigms that we utilize for various telemetry tasks. The first is a reactive monitoring scheme for packet loss detection\, that monitors only when needed\, by tailoring the measurement interval to when losses may occur. The second is a mechanism for finding heavy hitter flows of the recent past. Finally\, we explore the option of deleting and decaying a set-membership data structure to allow for more updated information to be maintained.  \n \nMario Baldi\, Fellow\nAMD Research and Advanced Development\nMario Baldi is a Fellow at AMD\, Research and Advanced Development\, and Associate Professor of Information Processing Systems (currently on leave) at Politecnico di Torino (Technical University of Turin)\, Italy. He has held various positions in startup and established companies in the computer networking industry\, as well as several visiting professorships at Universities in four continents\, during over 25 years of professional involvement in the computer networking domain. He authored over 150 scholarly papers on various networking related topics and two books\, and is co-inventor in 35 patents. \n“SmartNICs – P4’s Final Latest Frontier – Challenges and Opportunities Ahead”\nAbstract: While P4 emerged and got established as a language to program packet processing in switches\, it has since been successfully adopted in the context of programmable SmartNICs . This talk first overviews the widely differing architectures of programmable SmartNICs currently available on the market and then discusses the challenges we encounter when deploying P4 for programming them\, as well as the opportunities ahead.\n \nAgenda\n8:00-9:00 – Registration\n  \n9:00-9:10 – Welcome\nSandor Laki – Program Chair\, ELTE Eötvös Loránd University\nSlides\n  \n9:10-10:10 – Industrial Keynote – “SmartNICs – P4’s Final Latest Frontier – Challenges and Opportunities Ahead”\nMario Baldi\, Fellow\, AMD Research and Advanced Development\nSlides\n  \n10:10-10:30 – Coffee break\n  \n10:30-11:00 – “SCION Edge Router for Legacy IP Applications based on Intel Tofino”\nLars-Christian Schulz\, Robin Wehner\, David Hausheer (OVGU Magdeburg\, Germany)\nSlides | Paper\n  \n11:00-11:30 – “P4chaskey: An Efficient MAC Algorithm for PISA Switches”\nMartim Francisco\, Bernardo Ferreira\, Fernando M. V. Ramos (University of Lisbon\, Portugal)\, Eduard Marin (Telefonica Research\, Spain)\, Salvatore Signorello (Telefonica Research\, Spain; University of Lisbon\, Portugal)\nSlides | Paper\n  \n11:30-12:00 – “Deliberately Congesting a Switch for Better Network Functions Performance”\nMariano Scazzariello (KTH Royal Institute of Technology\, Sweden)\, Tommaso Caiazzi (Roma Tre University \,Italy)\, Marco Chiesa (KTH Royal Institute of Technology\, Sweden)\nSlides | Paper\n  \n12:00-14:00 – Lunch break\n  \n14:00-15:00 – Scientific Keynote: “Time-Aware Network Telemetry in the Data Plane”\nShir Landau Feibish\, Assistant Professor\, Open University of Israel \n15:00-15:30 – “Secure In-Band Network Telemetry for the SCION Internet Architecture on Tofino”\nRobin Wehner\, Tony John\, Lars-Christian Schulz\, David Hausheer (OVGU Magdeburg\, Germany)\nSlides | Paper\n  \n15:30-16:00 – Coffee break\n  \n16:00-16:30 – “Towards Real-Time Intrusion Detection in P4-Programmable 5G User Plane Functions”\nAristide Tanyi-Jong Akem (IMDEA Networks Institute\, Spain; Universidad Carlos III de Madrid\, Spain)\, Marco Fiore (IMDEA Networks Institute\, Spain)\nSlides | Paper\n  \n16:30-16:40 – Closing words\n  \nWORKSHOP ORGANISERS \nGeneral Chairs:\n– Fernando Ramos\, University of Lisbon\n– Muhammad Shahbaz\, Purdue University \nProgram Chairs:\n– Amedeo Sapio\, Amazon Web Services (AWS)\n– Sandor Laki\, ELTE Eötvös Loránd University \nPublicity Chair:\n– Csaba Györgyi\, ELTE Eötvös Loránd University / University of Vienna \nProgram Committee:\n– Andreas Kassler (Karlstad University\, Sweden; Technische Hochschule Deggendorf\, Germany)\n– Francesco Paolucci (CNIT\, Italy)\n– Stefan Schmid (TU Berlin\, Germany)\n– Christian E. Rothenberg (University of Campinas\, Brasil)\n– Noa Zilberman (Oxford University\, UK)\n– Gergely Pongrácz (Ericsson\, Hungary)\n– Andy Fingerhut (Cisco Systems\, USA)\n– Nik Sultana (Illinois Institute of Technology\, USA)\n– Sebastiano Miano (Politecnico di Milano\, Italy)\n– Sebastian Gallenmüller (TU Munich\, Germany)\n– Mingyuan Zang (Technical University of Denmark\, Denmark)\n– Masoud Hemmatpour (The Arctic University of Norway\, Norway)\n– Alan Zaoxing Liu (University of Maryland\, USA)
URL:https://p4.org/event/7th-european-p4-workshop-europ424/
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20241025T080000
DTEND;TZID=UTC:20241025T080000
DTSTAMP:20260417T020016
CREATED:20250912T220258Z
LAST-MODIFIED:20250915T225333Z
UID:10000123-1729843200-1729843200@p4.org
SUMMARY:Japan P4 Users Group
DESCRIPTION:The 2024 Japan P4 Users Group was hosted as a hybrid in-person and online event and included P4-related presentations and exhibits. View the agenda and resources. Talks were presented in Japanese and video can be accessed here.
URL:https://p4.org/event/japan-p4-users-group/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=UTC:20241003T080000
DTEND;TZID=UTC:20241003T080000
DTSTAMP:20260417T020016
CREATED:20250912T220242Z
LAST-MODIFIED:20251001T192054Z
UID:10000122-1727942400-1727942400@p4.org
SUMMARY:2024 P4 Workshop
DESCRIPTION:The 2024 P4 Workshop took place October 3rd\, and was hosted and sponsored by Google. This in-person event took place at Google’s Moffett Park Campus in Sunnyvale\, California and offered an opportunity for the P4 ecosystem to share knowledge and experiences with the broader community and to facilitate collaboration. \nView individual videos and slides on-demand from the event below! Or\, view YouTube Playlist. \nInvited Talks\n\n\n  \n\n\n\n\n \nTitle\nVideo\nSlides\n\n\n\n\n\nWelcome\, State of P4 & 2024 Distinguished Contributor Award \nAndy Fingerhut\, Principal Engineer\, Intel\n\n\n\n\n\n\nKeynote – Navigating Internet Research with P4: Solutions for Performance and Security\nMaria Apostolaki\, Assistant Professor of Electrical and Computer Engineering\, Princeton University\n\n\n\n\n\n\nFireside Chat with Martin Casado\nMartin Casado\, General Partner\, Andreessen Horowitz\nNate Foster\, Professor Computer Science\, Cornell University\n\n\n\n\n\n\nP4 on Hardware: The Future\nKonstantin Weitz\, Staff Software Engineer\, Google (Moderator)\nVipin Jain\, Sr Fellow Engineer\, AMD\nAnjali Singhai Jain\, Network Architect\, Intel\n\n\n\n\n\nIn-Depth Talks\n\n\n  \n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n\n\n\n\nPast\, Present and Future of P4\nDeb Chatterjee\, Sr Director Software Engineering\, Intel\n\n\n\n\n\n\nCompiler-assisted Kernel-based P4 Pipeline Offloading Using Intel IPU\nDeb Chatterjee\, Sr Director Software Engineering\, Intel\nNeha Singh\, Staff Software Engineer\, Intel\n\n\n\n\n\n\nTowards the Performant P4C\nAnton Korobeynikov\, Principal Software Engineer\, Compiler Development\, Access Softek Toolchains\n\n\n\n\n\n\nSupporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme\nBill Pontikakis\, Sr Research Associate\, Polytechnique Montréal\nFrançois-Raymond Boyer\, Professeur\, Polytechnique Montréal \n\n\n\n\n\n\n\nSONiC DASH on Intel IPU2100\nShweta Shrivastava\, Cloud Software Engineer\, Intel\nNamrata Limaye\, Director Software Engineering\, Intel \n\n\n\n\n\n\nInternals of the Intel Tofino Compiler\nGlen Gibb\, Compiler Engineer\, Intel\n\n\n\n\n\n\nP4-SpecTec – Mechanized Language Definition for P4\nJaehyun Lee\, Student\, KAIST\n\n\n\n\n\n\nCentralized Telemetry and Security Enforcement Using SONiC and P4\nShekher Bulusu\, Sr Manager Software Engineering\, GEICO\nPawan Ravi\, Sr Staff Engineer\, GEICO\nJames Choi\, Sr Engineering Manager\, GEICO\n\n\n\n\n\n\nModeling Hardware Blocks of Network ASICs using P4\nJean Tourrilhes\, Researcher\, HPE\n\n\n\n\n\n\nIn-Memory Key-Value Store Live Migration with NetMigrate\nZeying Zhu\, PhD Student\, University of Maryland\n\n\n\n\n\n\nP4-Based Automated Reasoning (P4-BAR) for the (Networking) Masses!\nSteffen Smolka\, Staff Software Engineer\, Google\nJonathan DiLorenzo\, Software Engineer\, Google\n\n\n\n\n\n\nScaling P4-Based Automated Reasoning (Performance and Coverage)\nAli Kheradmand\, Senior Software Engineer\, Google\nMeghana Sistla\, PhD Student\, University of Texas at Austin\n\n\n\n\n\n\nP4HIR: Toward Bridging P4C with MLIR\nBili Dong\, Software Engineer\, Google\n\n\n\n\n\nDemos\n\n  \n\n\n\n\n \nTitle\n \nAbstract\n\n\n \n\n\n\nSONiC DASH on Intel IPU2100\nNamrata Limaye\, Director Software Engineering\, Intel \n\n\n \n\n\n\nData Center Routing GEICO SDN Controller and GEICO SONiC Using P4\nSunil Kumar Rawookar\, Staff Engineer\, GEICO Tech\n\n\n \n\n\n\nOffload NAT and Routing onto Intel IPU Using P4-TC\nNeha Singh\, Staff Software Engineer\, Intel\n\n\n \n\n\n\nP4 IDE: An Integrated Development Environment for P4-based Data Plane Development\nNamrata Limaye\, Director Software Engineer\, Intel\n\n\n \n\n\nP4Docker: Simplifying P4 Switch Testbeds with Docker Integration \nLucas Trombeta\, PhD Candidate\, Federal University of ABC (UFABC)\n\n\n \n\n\n\nSupporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme\nBill Pontikakis\, Sr Research Associate\, Polytechnique Montréal\nFrançois-Raymond Boyer\, Professeur\, Polytechnique Montréal \n\n\n\n\nPoster\n\n  \n\n\n\n\n \nTitle\nAbstract\n\n\n\n\n\n\nBabel: The Tower So Far\nVictor Rios\, Software Engineer\, Google\n\n\n\n\nGeneral Chair – Nate Foster \nProgram Co-Chairs – Andy Fingerhut\, Muhammad Shahbaz \nProgram Committee\n– Jehandad Khan\, AMD\n– Ori Rottenstreich\, Technion\n– Vishal Shrivastav\, Purdue University\n– Gianni Antichi\, Politecnico di Milano and Queen Mary University of London\n– Ben Pfaff\, Feldera\n– Ajay Lotan Thakur\, Intel Corp\n– Victor Liu\, University of Michigan\n– Vladimir Gurevich\, P4ica\n– Tushar Swamy\, unaffiliated\n– Yiming Qiu\, University of Michigan\n– Amedeo Sapio\, Amazon Web Services\n– Lavanya Jose\, Google
URL:https://p4.org/event/2024-p4-workshop-postevent/
CATEGORIES:Events
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DTSTART;TZID=UTC:20240905T090000
DTEND;TZID=UTC:20240905T090000
DTSTAMP:20260417T020016
CREATED:20250912T215847Z
LAST-MODIFIED:20250915T225417Z
UID:10000081-1725526800-1725526800@p4.org
SUMMARY:2024 P4 GSoC Projects - Webinar
DESCRIPTION:Thursday\, September 5\, 2024\n9:00am Pacific \nView Video \nLearn about the four exciting projects hosted by the P4 Language Organization as part of Google‘s Summer of Code (GSoC) 2024. Each of the project contributors present their projects followed by a short discussion. \nP4 Projects in GSoC\n\nView Project Details\nImproving the documentation of the P4 Compiler\nContributor: Adarsh Rawat\, Graphic Era Deemed to be University\nMentors: Fabian Ruffy\, Davide Scano \nBuilding a Formatter for the P4 Language\nContributor: Nitish Kumar\, Indian Institute of Technology Kharagpur\nMentors: Bili Dong\, Fabian Ruffy \nIntroducing PNA support to BMv2\nContributor: Rupesh Chiluka\, University of Hyderabad (UoH)\nMentors: Hari Thantry\, Debobroto Das Robin \nP4-Enabled Container Migration in Kubernetes\nContributor – Stanislav Korosin\, Technische Universität Berlin\nMentors: Davide Scano\, Radostin Stoyanov
URL:https://p4.org/event/2024-p4-gsoc-projects-webinar/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=UTC:20240821T080000
DTEND;TZID=UTC:20240821T080000
DTSTAMP:20260417T020016
CREATED:20250912T215846Z
LAST-MODIFIED:20250915T225425Z
UID:10000080-1724227200-1724227200@p4.org
SUMMARY:P4 Developer Days - NSF Cybertraining Project
DESCRIPTION:August 21\, 2024 | 8:00am Pacific\nView Recording\nA key barrier to the faster adoption of programmable data planes (e.g.\, P4 switches\, SmartNICs\, end-hosts) is the lack of engaging training materials. This NSF Cybertraining project aims to address this challenge by developing hands-on virtual labs (vLabs) for online instruction. These vLabs will be deployed on FABRIC\, an NSF-funded international infrastructure for research at scale\, and on the Academic Cloud\, a training and research cloud system maintained by the University of South Carolina. The team has already created approximately 30 vLabs on BMv2\, the P4 software switch. The project will now focus on open-source technologies related to SmartNICs and end-host stacks (e.g.\, PNA\, P4-DPDK\, P4TC\, P4-eBPF\, etc.). The developed vLabs will be open-source and available to the community. Learners will be provided with detailed laboratory manuals and access to the training platforms\, which are accessible from the Internet using a regular web browser (no SSH or installations required). \nPresenters \nElie Kfoury\, University of South Carolina\nJorge Crichigno\, University of South Carolina
URL:https://p4.org/event/p4-developer-days-nsf-cybertraining-project/
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DTSTART;TZID=UTC:20240429T080000
DTEND;TZID=UTC:20240501T080000
DTSTAMP:20260417T020016
CREATED:20250912T220241Z
LAST-MODIFIED:20250915T225437Z
UID:10000120-1714377600-1714550400@p4.org
SUMMARY:ONE Summit 2024: P4-Based Automated Reasoning
DESCRIPTION:  \nCheck out the video and slides by P4 TST member Steffen Smolka\, “P4-based Automated Reasoning” which was featured at The Linux Foundation’s One Summit 2024. In his talk he discusses how P4 is now being used as a specification language for network programmable and non-programmable pipelines. He discusses how Google and others have been leveraging such machine-readable\, unambiguous\, vendor-agnostic specifications of their switches to increase network reliability and development as well as allow the SDN controller to interoperate seamlessly with switches form different vendors. \n  \nView Video \nReview Slides
URL:https://p4.org/event/one-summit-2024-p4-based-automated-reasoning/
CATEGORIES:Events
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DTSTART;TZID=UTC:20240402T080000
DTEND;TZID=UTC:20240402T080000
DTSTAMP:20260417T020016
CREATED:20250912T220231Z
LAST-MODIFIED:20250915T225500Z
UID:10000119-1712044800-1712044800@p4.org
SUMMARY:P4 Open Source Developer Days: P4 Traffic Generator and Analyzer
DESCRIPTION:April 2nd 2024 \nIn case you missed it\, you can now watch the recording of the recent P4 Developer Days Talk by Steffen Lindner (University of Tuebingen) on the P4TG traffic generator and analyzer. \n“We present P4TG\, an open-source P4-based traffic generator (TG) which runs on the programmable Intel Tofino ASIC. In generation mode\, P4TG is capable of generating traffic up to 1 Tb/s split across 10x 100 Gb/s ports. Thereby it measures rates directly in the data plane. Generated traffic may be fed back from the output to the input ports\, possibly through other equipment\, to record packet loss\, packet reordering\, inter-arrival times (IATs) and sampled round trip times (RTTs). Further\, it supports VLAN\, QinQ\, and MPLS encapsulation. In analysis mode\, P4TG measures rates on the input ports and IATs\, and forwards traffic through its output ports. Existing software or P4-based traffic generators either lack the required accuracy\, do not support high data rates\, or do not provide sufficiently integrated measurement capabilities.”
URL:https://p4.org/event/p4-open-source-developer-days-p4-traffic-generator-and-analyzer/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20231208T080000
DTEND;TZID=UTC:20231208T080000
DTSTAMP:20260417T020016
CREATED:20250912T220230Z
LAST-MODIFIED:20250915T225515Z
UID:10000118-1702022400-1702022400@p4.org
SUMMARY:Euro P4 2023
DESCRIPTION:EuroP4 2023 took place December 8th in conjunction with ACM CoNEXT 2023 in Paris (France). This event brought together networking researchers and practitioners to discuss cutting-edge\, P4-enabled research and P4-based technology. The workshop provided a venue for presenting and discussing research and projects related to P4\, as well as for more broadly discussing the needs of this research community. The workshop aimed to forge new connections between researchers who already work with P4\, introduce more networking researchers to the P4 community\, and seed future top-tier publications\, innovation and contributions to this community.\nView proceedings from the 2023 EuroP4 Workshop \n  \nSession 1: P4 Networking\n\nLANTERN: Layered Adaptive Network Telemetry Collection for Programmable Data Planes\nKaiyu Hou (Alibaba Cloud)\, Dhiraj Saharia (Georgetown University)\, Vinod Yegneswaran (SRI International)\, Phil Porras (SRI International) \n\nAbstract: \nManaging next-generation enterprise networks requires collecting and analyzing enormous volumes (tens of Tbps) of network traffic data in real time to detect potential anomalies\, classify attacks\, identify root causes\, and rapidly deploy effective mitigations. Conducting robust and scalable analysis on such traffic volumes is a daunting ”haystack” problem that demands intelligent strategies to winnow traffic to extract and pinpoint ”needles” of interest. Recent advances in software-defined networking and programmable dataplanes\, that enable dynamic reconfiguration of switching hardware to adapt to changing traffic conditions\, provide a foundational building block. However\, they lack the resources and programming primitives for complex computational models. \nToward that end\, we present LANTERN\, a layered and adaptive network telemetry system that facilitates joint collection and analysis of network traffic at multiple resolutions in coordination with the controller. Our design offloads complex machine-learning analysis to the controller\, while still enabling proactive telemetry refinement and reactive mitigation triggers at the data-plane level. We evaluate our layered approach by replaying a labeled CIC-IDS attack dataset through both software and hardware P4 switches. LANTERN is able to detect most anomalies\, accurately classify them\, and introduces negligible switching overhead (1% latency). \nRead Paper | View Slides \n  \nPer Priority Data Rate Measurement in Data Plane \nHabib Mostafaei (Eindhoven University of Technology)\, Georgios Smaragdakis (Delft University of Technology) \nAbstract: \nMany applications\, such as video streaming\, congestion control\, and server selection\, can benefit when the data rate of different priority groups between two endpoints is accurately estimated over the end-to-end path. With the introduction of programmable networks\, e.g.\, P4\, it is now possible to offload the measurements to the data plane of intermediate devices. Recently\, tools have been developed to react to changes in available bandwidth\, but a tool to accurately estimate end-to-end per-priority data rates needs to be added. This motivates us to design and implement a new end-to-end and per-priority data rate estimation tool\, PrioMeter. PrioMeter can accurately report the data rate per priority group of flows in programmable networks using high-precision timestamps for arbitrary traffic scales. PrioMeter leverages two primitives: quantization and truncation\, to achieve its goals. We implement PrioMeter in P4 and test it on BMv2 switches\, and our preliminary results using NS3 simulations show that it can accurately estimate the data rate of different priority flows with minimal overhead. \nRead Paper | View Slides \n  \nCryptographic Path Validation for SCION in P4 \nLars-Christian Schulz (OVGU Magdeburg)\, Robin Wehner (OVGU Magdeburg)\, David Hausheer (OVGU Magdeburg) \nAbstract: \nSCION has been proposed as a new Internet architecture addressing security and scalability shortcomings in the current Internet. Multiple real-world deployments of SCION exist already\, nevertheless few hardware implementations of SCION routers are available. \nIn this paper\, we implement a SCION border router on a programmable 12.8 Tbit/s Intel Tofino 2 switch. Our router utilizes the multiple separately programmable packet pipelines of Tofino 2 in order to compute SCION’s AES-CMAC-based hop authenticators in general-purpose P4 without assistance from specialized hardware. \nUsing three out of four available pipelines\, we achieve 394.7 Gbit/s throughput per port on 8 ports for a total of 3.16 Tbit/s capacity. Using only two pipelines we still achieve line rate throughput on 4 ports for a total of 1.58 Tbit/s capacity. To our knowledge there is no other SCION router including the AES-CMAC validation that offers a comparable performance. \nRead Paper | View Slides \n\n  \n\n\nSession 2 – P4 Control & Targets\n\n\nIntroducing P4TC – A P4 Implementation on Linux Kernel using Traffic Control\nJamal Hadi Salim (Mojatatu Networks)\, Deb Chatterjee (Intel Corporation)\, Victor Nogueira (Mojatatu Networks)\, Pedro Tammela (Mojatatu Networks)\, Tomasz Osinski (Intel Corporation)\, Evangelos Haleplidis (Mojatatu Networks)\, Balachandher Sambasivam (Intel Corporation)\, Usha Gupta (Intel Corporation)\, Komal Jain (Intel Corporation)\, Sosutha Sethuramapandian (Intel Corporation) \nAbstract: \nThe networking industry is at an inflection point with ever increasing network link capacities coupled with the presence of programmable hardware ASICs. These set of circumstances call out for a robust approach to hardware and software co-existence for network programmability. \nP4TC is a P4 Linux kernel-native implementation on top of the Linux Traffic Control (TC) infrastructure that provides a vendor-neutral\, kernel-independent and architecture-independent interface for Match-Action packet processing compatible with the P4 specification. P4TC facilitates both a hardware datapath and a functionally equivalent kernel eBPF-assisted software datapath making it ideal to deal with both high speed links and programmable hardware. \nIn this paper\, we describe the goals and motivation of P4TC\, the design and architecture as well as illustrate the different concepts of the P4TC infrastructure via an example of a simple L2 switch. \nRead Paper | View Slides \n  \n\nNAP: Programming data planes with Approximate Data Structures\nMengying Pan (Princeton University)\, Hyojoon Kim (University of Virginia)\, Jennifer Rexford (Princeton University)\, David Walker (Princeton University) \nAbstract: \nMany applications that run on programmable data planes rely on approximate data structures\, due to insufficient in-network memory. However\, programming with approximate data structures is challenging because it requires (1) expertise in streaming algorithms to select the data structures that best match an application’s requirements\, (2) meticulous configuration to minimize approximation error while fitting within the hardware constraints\, and (3) proficiency in the low-level P4 language. To address these issues\, we propose NAP\, a high-level network programming language. The core of NAP is the versatile approximate dictionary abstraction that captures a wide range of compact data structures\, while allowing programmers to simply specify the kinds of error an application can tolerate. We demonstrate the language’s expressiveness\, conciseness\, and efficiency through a variety of network applications\, each compiling to P4 for the Intel Tofino in less than a second and featuring 25X–50X fewer lines of code compared to the P4 output. We evaluate an approximate stateful firewall written in NAP with real campus traffic\, achieving performance consistent with the predicted accuracy. \nRead Paper | View Slides \n  \nP4EAD: Securing the In-band Control Channels on Commodity Programmable Switches \nArchit Bhatnagar (Birla Institute of Technology & Science\, Pilani)\, Xin Zhe Khooi (National University of Singapore)\, Cha Hwan Song (National University of Singapore)\, Mun Choon Chan (National University of Singapore) \nAbstract: \nConventionally\, the control channel on network switches has always been out-of-band. With the emergence of high-performance systems built upon programmable switches\, the out-of-band control channel has become the bottleneck. Thus\, there is an emerging trend of implementing the control channel in the data path (i.e.\, in-band) on programmable switches to achieve high throughput and low-latency control actions. However\, the use of in-band control channels comes with the risk of security vulnerabilities that have not been explored in prior literature. In this paper\, we present P4EAD\, a cryptographic primitive to secure the in-band control channels on programmable switches entirely in the data plane. This ensures the integrity\, authenticity\, and confidentiality of in-band control messages. We conduct micro-benchmarks on P4EAD and demonstrate its integration with an existing high-performance in-band control framework\, showcasing minimal performance impact when securing the control channel. \nRead Paper | View Slides \n\n  \n\n\nPosters and Demos Session\nPoster: High-Speed Per-Packet Checksums on the Intel Tofino\nDavid Grölle (OVGU Magdeburg)\, Lars-Christian Schulz (OVGU Magdeburg)\, Robin Wehner (OVGU Magdeburg)\, David Hausheer (OVGU Magdeburg) \nAbstract: \nPath-aware networking has introduced new possibilities to monitor and control network access and solved a multitude of modern-day Internet security issues. Being able to authorize usage of specific paths enables network operators to offer high-quality services to customers requiring highly reliable network access. \nCurrently\, securing a network path or an end host is only possible by using high-level solutions like VPNs. With EPIC-HP (Every Packet Is Checked – Hidden Path)\, it has been shown that it is possible to move this functionality down into the network itself. EPIC-HP extends the path-aware Internet architecture SCION by offering per-packet checksums\, adding authentication to network traffic. This is used to combat DoS attacks on the network’s end hosts and give high-priority access to specific end users. In this paper\, we show that it is possible to implement the functionality of EPIC-HP along with SCION on the Intel Tofino 2 ASIC. EPIC-HP requires AES-based MAC verification with per-path keys in the data plane. By using the multi-pipeline structure of the Tofino\, we implemented the required AES and AES-CMAC cryptography using three pipes of the switch’s total four independent pipes. \nThe throughput we achieve is an order of magnitude above the data rates previously achieved for EPIC-HP and is a significant step towards a more secure Internet. \nRead Paper \n  \nPoster: P4DME: DNS Threat Mitigation with P4 In-Network Machine Learning Offload \nJuan Vanerio (University of Vienna)\, Csaba Györgyi (University of Vienna)\, Stefan Schmid (TU Berlin\, Fraunhofer SIT) \nAbstract: \nThe ever-evolving cybersecurity landscape demands innovative solutions to safeguard critical network infrastructure such as the Domain Name System (DNS). This paper presents P4DME\, a novel approach that harnesses the potential of Machine Learning (ML) in conjunction with P4 programmable switches to tackle DNS threats efficiently. P4DME’s primary benefit lies in offloading filtering from resource-intensive ML processing tasks on dedicated servers. This offloading boosts the overall traffic throughput that can be inspected or achieves the same throughput with reduced resource consumption while preserving the servers’ capabilities for high-performance threat identification. This work uses P4-based in-network elements to handle crucial DNS threats\, dynamic white- and blacklisting\, and an online popularity-based anomaly detection heuristic. The latter serves as a trigger for dedicated ML-based inspection. Furthermore\, we introduce in-network mitigation filters updated through the control plane to provide adaptable and responsive threat mitigation. Preliminary simulation results show more than 99.9% offload ratio at 5% increased False Negative Ratio. \nRead Paper \n  \nPoster: Maintaining Sets With Deletions in the Data Plane \nJonathan Diamant (The Open University of Israel)\, Shir Landau Feibish (The Open University of Israel) \nAbstract: \nSets are one of the most fundamental data types in Computer Science\, and data structures used to maintain sets are used in many algorithms. These structures normally support three basic operations: insertion\, look-up (i.e. set-membership query)\, and deletion. The most common set-membership data structure used in the data plane is the Bloom Filter (BF). While BFs are relatively easy to adapt to the data plane\, they offer a limited set-membership functionality as they do not support deletions. If deletions are required\, a Counting Bloom Filter (CBF) (which maintains counters instead of bits) may be used. Yet\, if a key was inserted multiple times\, multiple deletions would be needed to completely remove the key from the structure. We present MEM-D\, a fast and lightweight set-membership data structure for the data plane\, which supports all three operations: look-up\, insertion\, and deletion. MEM-D supports the uniqueness property\, meaning that a key would be removed with a single deletion operation even if it was inserted multiple times. MEM-D provides a false positive (FP) error rate similar to the rate of the standard BF and additionally may incur a small false negative (FN) error. We have implemented MEM-D on a hardware Tofino target using P4. To the best of our knowledge\, MEM-D is the first data structure for set-membership in the data plane\, which supports deletion. \nRead Paper \n  \n\nPoster: Adaptive In-Network Inference using Early-Exits\nHeewon Kim (Korea University)\, Seongyeon Yoon (Korea University)\, Sangheon Pack (Korea University) \nAbstract: \nIn-network (or on-path) inference over programmable data planes allows fast and low-overhead inference in deep neural networks. In this work\, we propose an adaptive approach to strike the balance between accuracy and processing cost. To be specific\, the confidence score is evaluated at the end of each layer\, and an early exit is triggered if the confidence score is sufficiently high. We implement this early-exit scheme over BMv2 software switches and the results demonstrate that the proposed scheme successfully controls the trade-off by making use of the confidence score. \nRead Paper \n  \nDemo: Enabling DNN-Based Inference in the Network Data Plane \nSiddhartha (AMD)\, Justin Tan (AMD & NUS)\, Rajesh Bansal (AMD)\, Chee Chung Chan (AMD)\, Yuta Tokusashi (AMD)\, Yew Kwan Chong (AMD)\, Haris Javaid (AMD)\, Mario Baldi (AMD) \nAbstract: \nAdvancements in programmable packet processing technologies have fostered innovation across a range of networking applications. Integration of deep neural networks (DNN) in the network data plane\, however\, has remained largely unaddressed due to the high compute requirements of the underlying algebraic kernels. In this paper\, we show how P4 packet processing pipelines can be augmented with DNN inference engines on devices readily available in the market today. We share a network security case study\, where we train a DNN-based anomaly detector that classifies active traffic flows as either malicious or benign using per-packet inference. Our implementation runs on an AMD AlveotextsuperscriptTM U250 FPGA accelerator card\, and is capable of servicing network traffic of up to approx~98~Mpps on 100~GbpE links. \nRead Paper \n  \nWorkshop General Chairs\nFernando Ramos\, University of Lisbon\nMuhammad Shahbaz\, Purdue University \nProgram Chairs\nVladimir Gurevich\, P4ica\nSalvatore Signorello\, Telefonica Research\, Spain \nPublicity Chairs\nDenise Barton\, ONF\nSandor Laki\, Eötvös Loránd University \nProgram Committee\nAlan Lo\,  NVIDIA\nAlan Zaoxing Liu\, University of Maryland\nAndy Fingerhut\, Intel\nAnirudh Sivaraman\, New York University\nChristian Esteve Rothenberg\, University of Campinas\nDaehyeok Kim\, University of Texas at Austin\nDavide Sanvito\, NEC Labs\nEnnan Zhai\, Alibaba Cloud\nGianni Antichi\, Politecnico di Milano & Queen Mary University of London\nJiarong Xing\, Rice University\nMario Baldi\, AMD & Politecnico di Torino\nNate Foster\, Cornell University\nNik Sultana\, Illinois Institute of Technology\nRobert Soulé\, Yale University\nShir Landau Feibish – The Open University of Israel \n 
URL:https://p4.org/event/euro-p4-2023/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=UTC:20230424T080000
DTEND;TZID=UTC:20230425T080000
DTSTAMP:20260417T020016
CREATED:20250912T220028Z
LAST-MODIFIED:20250915T225525Z
UID:10000100-1682323200-1682409600@p4.org
SUMMARY:2023 P4 Workshop
DESCRIPTION:The P4 Workshop is an opportunity for the P4 ecosystem to share knowledge and experiences with the broader community and to facilitate collaboration. The workshop incorporates insights and perspectives from the P4 community across the following key areas: \n\nP4 language\nP4 targets\nP4 tool chain\nP4 use cases & applications\nControl plane or network OS for P4 targets\nExtensions to P4\nCross-cutting work between P4 and related systems such as eBPF and service meshes.\n\nView individual videos and slides below! Or\, view YouTube playlist. \nKeynotes\n\n\n\n\n\n \nTitle\nVideo\nSlides\n\n\n\n\n\n\nWelcome & State of P4\nMina Tahmasbi Arashloo\, Program Chair\, University of Waterloo\nAndy Fingerhut\, Principal Engineer\, Intel\n\n\n\n\n\n\nFireside Chat with Nick McKeown\nNick McKeown\, P4 Co-founder & Evangelist\nLarry Peterson\, Chief Scientist\, ONF\n\n\n\n\n\n\nDeveloping Real World Applications Using P4-Based Architecture\nKrishna Doddapaneni\, Corporate Vice President\, AMD Pensando\n\n\n\n\n\n\nP4 HAL for Network Virtualization\nParveen Patel\, Google Cloud\, Senior Director Engineering\, Google Cloud\n\n\n\n\n\n\nThe Power of Fully-Specified Data Planes\nRob Sherwood\, Chief Technology Officer\, NEX Cloud Networking Group\, Intel\n\n\n\n\n\n\nFrom Programmability to Fungibility\nAng Chen\, Assistant Professor Computer Science\, Rice University\n\n\n\n\n\n\nCan SmartNICs Help Accelerate Distributed Systems?\nArvind Krishnamurthy\, Short-Dooley Professor\, Paul G. Allen School of Computer Science & Engineering\, University of Washington\n\n\n\n\n\nIn-Depth Talks\n\n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n\n\n\n\nEscaping Babel: The Flow Must Go On\nVictor Rios\, Google\n\n\n\n\n\n\nOpenConfig Co-Existence with P4 Using TDI\nJames Choi\, Cloud SW Architect\, Intel\n\n\n\n\n\n\nFormalizing and Extending P4’s Type System\nParisa Ataei\, Postdoc\, Cornell University\n\n\n\n\n\n\nEffective DGA Family Classification Using a Hybrid Shallow and Deep Packet Inspection Technique on P4 Programmable Switches\nAli AlSabeh\, University of South Carolina\n\n\n\n\n\n\nSegment Routing Proxy Device implemented Using P4 on FPGA with Zero CPU Overhead\nMiroslaw Walukiewicz\, Intel\n\n\n\n\n\n\nHardware Offload Driver with P4-TC\nAnjali Singhai Jain\, Network Architect\, Intel\nNamrata Limaye\, Intel\n\n\n\n\n\n\nP4TC: Linux Kernel P4 implementation Approaches and Evaluation\nDeb Chatterjee\, Intel\nJamal Hadi Salim\, Mojatatu Networks\n\n\n\n\n\n\nAugmenting P4-DPDK Software Pipelines with Accelerators: the IPsec Use Case\nAndy Fingerhut\, Intel\n\n\n\n\n\nLightning Talks\n\n  \n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n \n\n\n\nIntent-based Platform Leverages Programmable Networking for Optimizing Edge\nDave Duggal\, Founder/CEO\, EnterpriseWeb\nWilliam Malyk\, Chief System Architect\, EnterpriseWeb\n\n\n\n \n\n\n\nA Language Engineering Approach to Support the P4 Coding Ecosystem\nAlexandre Lachance\, Graduate Student\, McMaster University\n\n\n\n \n\n\n\nEnhancing Blockage Detection and Handover on 60 GHz Networks with P4 Programmable Data Planes\nAli AlSabeh\, Computer Science PhD Student\, University of South Carolina\n\n\n\n \n\n\n\nP4MS: Leveraging Passive Measurements from P4 Switches to Dynamically Modify a Router’s Buffer Size\nJose Gomez\, Graduate Assistant\, University of South Carolina\n\n\n\n\n\nP4 Working Group Update\n\n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n \n\n\n\nWhat’s New in P4-16\nMihai Budiu\, P4 Language Design Working Group Co-Chair\n\n\n\n \n\n\n\nP4.org Architecture Work Group\nMario Baldi\, P4 Architecture Working Group Co-Chair\nAndy Fingerhut\, P4 Architecture Working Group Co-Chair\n\n\n\n \n\n\n\nP4 API Working Group Annual Wrap-up\nChris Sommers\, API Working Group Co-Chair\nSteffen Smolka\, API Working Group Co-Chair\n\n\n\n\n\nDemos\n\n  \n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n \n\n\n\nA Language Engineering Approach to Support the P4 Coding Ecosystem\nAlexandre Lachance\, Graduate Student\, McMaster University\n\n\n\n \n\n\n\nDemo to Offload Networking Pipeline on Intel IPU E2000 Using P4 Control Plane\nNupur Uttarwar\, Cloud Software Engineer\, Intel\nNamrata Limaye\, Senior Engineering Manager\, Cloud Software\, Intel\n\n\n\n \n\n\n\nEnabling P4 hands-on Training Using Hardware Switches in a Cloud System at the University of South Carolina\nJose Gomez\, Graduate Assistant\, University of South Carolina\n\n\n\n \n\n\n\nEnhancing Blockage Detection andHandover on 60 GHz Networks with P4 Programmable Data Planes\nAli AlSabeh\, Research Assistant\, University of South Carolina\n\n\n\n\n\nPosters\n\n  \n\n\n\n\n \nTitle\nDetails\n\n\n\n\n\n\nA Testbench for Testing Programmable Traffic Managers in a Software Environment\nBill Pontikakis\, Research Associate\, Polytechnique Montreal\n\n\n\n\n\nCasual Network Telemetry\nYunhe Liu\, Research Assistant\, Cornell University\n\n\n\n\n\nEnhancing Blockage Detection and Handover on 60 GHz Networks with P4 Programmable Data Planes\nAli AlSabeh\, Research Assistant\, University of South Carolina\n\n\n\n\n\nExtending the P4 Language to Facilitate the Use of Stateful Constructs\nJorg Ehmer\, Polytechnique Montreal\n\n\n\n\n\nIntent-based Platform Leverages Programmable Networking for Optimizing Edge\nDave Duggal\, Founder/CEO\, EnterpriseWeb\nWilliam Malyk\, Chief System Architect\, EnterpriseWeb
URL:https://p4.org/event/2023-p4-workshop/
CATEGORIES:Events
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