2022 P4 China Open Programmable Network Summit
2022-12-05 08:00 UTC
The 2022 P4 China Open Programmable Network Summit brings together experts, scholars, business executives, and technical executives to discuss the practice, development and trends of open programmable networks, P4 languages, and innovative applications of the network. Universities, research institutes and companies in the academic salon will also share P4 scientific research experiences and collaboration. In addition, the summit hosts an exhibition area.
The event is sponsored by Intel® and co-organizer, Jiangsu Future Network Innovation Research Institute.
The Intel® 2022 P4 China Hackathon will be held in conjunction with the 2022 P4 China Open Programmable Network Summit. Learn more and register separately for this event.

Euro P4 2022
2022-12-09 08:00
EuroP4 2022 took place December 9th and was held in conjunction with CoNEXT 2022 (December 6-9, 2022) in Rome, Italy.
The 5th European P4 Workshop (EuroP4) brought together networking researchers to discuss cutting-edge P4-based research and projects, P4-based tools, and the needs of the community. The workshop created an opportunity to forge connections between researchers, introduce more networking researchers to the P4 community, and seed future top-tier publications and innovation.
View proceedings from the Euro P4 Workshop.
SESSION: Security
BACKORDERS: Using Random Forests to Detect DDoS Attacks in Programmable Data Planes
Bruno Coelho (Federal University of Rio Grande do Sul (UFRGS)), Alberto Schaeffer-Filho (Federal University of Rio Grande do Sul (UFRGS)
Networks and the services they support form the communication backbone of our society, and it is important that potential Distributed Denial of Service (DDoS) attacks are detected quickly, in order to avoid or minimize the impact they may have on the availability of services. Recent technological advances in programmable networks – specifically the programmability of data planes in switches and routers, have made available new ways of detecting such attacks. By relying on this newfound possibility, this paper proposes the utilization of a Random Forest (RF) to aid in quickly and accurately detecting DDoS attacks in a programmable switch. Random forests utilize several classification trees, each of them for independently classifying an input as one of a set of classes. Here, each decision tree will classify a network flow as potentially malicious, i.e. part of a DDoS attack, or a legitimate user flow. Despite utilizing multiple classification trees to improve accuracy, random forests are relatively lightweight, with each tree requiring few and simple computations to arrive at a classification. Our results show that even small RFs, requiring as few as 63 match+action table entries, can achieve F1-Scores of over 90%.
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A P4-Based Content-Aware Approach to Mitigate Slow HTTP POST Attacks
Chih-Yu Hsieh (National Taiwan University), Hong-Yen Chen (National Taiwan University), Shan-Hsiang Shen (National Taiwan University of Science and Technology), Chen-Hsiang Hung (National Taiwan University), Tsung-Nan Lin (National Taiwan University)
A slow HTTP POST attack is an application-layer distributed denial-of-service attack targeting web servers. The attacker simulates a legitimate user with a slow network speed and continues to send requests, resulting in server resources being unavailable for a long time to other users. The similarity to legitimate behavior makes it challenging to identify such attack traffic. To address this issue, this paper proposes a responsive defense mechanism that exploits programmable network devices to identify attack traffic based on HTTP headers. With information that is not available from legacy network devices, this method can identify different types of requests and apply limitations. This approach achieves a distributed, source-based defense capability by utilizing data plane programmability, making it a scalable solution. The simulation results show that the approach is effective and accurate against slow HTTP POST attacks.
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On Implementing ChaCha on a Programmable Switch (Short Paper)
Yutaro Yoshinaka (Osaka University), Junji Takemasa (Osaka University), Yuki Koizumi (Osaka University), Toru Hasegawa (Osaka University)
This paper presents an implementation of a practical cryptographic primitive based on ChaCha on a Tofino programmable switch. A key challenge is optimizing the implementation by leveraging the structure of ChaCha operations and hardware features of Tofino. Our implementation outperforms the AES-based approach in terms of performance and small memory footprint and achieves up to 203 Gbps of throughput.
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SESSION: Architecture and Language
Reducing P4 Language’s Voluminosity using Higher-Level Constructs
Albert Gran Alcoz (ETH Zürich), Coralie Busse-Grawitz (ETH Zürich), Eric Marty (ETH Zürich), Laurent Vanbever (ETH Zürich)
Over the last years, P4 has positioned itself as the primary language for data-plane programming. Despite its constant evolution, the P4 language still “suffers” from one significant limitation: the voluminosity of its code. Today, P4 users overcome this limitation by relying on templating tools, hand-crafted scripts, and complicated macros. Unfortunately, these methods are not optimal: they make the development process difficult and do not generalize well beyond one codebase.
In this work, we propose reducing the voluminosity of P4 code by introducing higher-level language constructs. We present O4, an extended version of P4, that includes three such constructs: arrays (which group same-type entities together), loops (which reduce simple repetitions), and factories (which enable code parametrization).
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Compiling Packet Programs to dRMT Switches: Theory and Algorithms
Balázs Vass (Budapest University of Technology and Economics), Ádám Fraknói (Eötvös Loránd University), Erika Bérczi-Kovács (Eötvös Loránd University), Gábor Rétvári (Budapest University of Technology and Economics)
A critical step in P4 compilation is finding an efficient mapping of the high-level P4 source code constructs to the physical resources exposed by the underlying hardware, while meeting data and control flow dependencies in the program. In this paper, we take a new look at the algorithmic aspects of this problem, with the motivation to understand the fundamental theoretical limits and obtain better P4 pipeline embeddings in the dRMT (disaggregated Match-Action Table) switch architecture. We report mixed results. We find that optimizing P4 program embedding for maximizing throughput is computationally intractable even when some architectural constraints are relaxed, and there is no hope for a tractable approximation with arbitrary precision unless P = NP. At the same time, we find that the maximal throughput embedding is approximable in quasi-linear time with a small constant bound. Our evaluations show that the proposed algorithm outperforms the heuristics of prior work both in terms of throughput and compilation speed.
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In-Network Fractional Calculations using P4 for Scientific Computing Workloads
Shivam Patel (Illinois Institute of Technology), Rigden Atsatsang (Illinois Institute of Technology), Kenneth M Tichauer (Illinois Institute of Technology), Michael H L S Wang (Fermilab), James B Kowalkowski (Fermilab), Nik Sultana (Illinois Institute of Technology)
Recent P4 research has motivated the need for in-network fractional calculations to support functions in Networking (for calculations related to active queue management and load balancing) and in Machine Learning. The P4 language and ASICs do not natively support fractional types (e.g., float).

This paper re-thinks the foundation of in-network fractional calculation and proposes a new approach that is more resource conscious and is straightforward to encode in P4. Instead of floating-point, it uses a fixed-point encoding of numerals; and instead of sampling functions into tables it uses Taylor Approximation to reduce data-plane calculations to simple arithmetic over pre-calculated coefficients, requiring constant space and linear time. The paper describes and evaluates a P4 code synthesis algorithm that allows users to trade-off switch resources for accuracy, grounded on an application of a well-understood mathematical theory. It describes how to encode π and various functions including cos, log and exp.
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HOL4P4: Semantics for a Verified Data Plane
Anoud Alshnakat (KTH Royal Institute of Technology), Didrik Lundberg (KTH Royal Institute of Technology, Saab AB), Roberto Guanciale (KTH Royal Institute of Technology), Mads Dam (KTH Royal Institute of Technology), Karl Palmskog (KTH Royal Institute of Technology)
We introduce a formal semantics of P4 for the HOL4 interactive theorem prover. We exploit properties of the language, like the absence of call by reference and the copy-in/copy-out mechanism, to define a heapless small-step semantics that is abstract enough to simplify verification, but that covers the main aspects of the language: interaction with the architecture via externs, table match, and parsers. Our formalization is written in the Ott metalanguage, which allows us to export definitions to multiple interactive theorem provers. The exported HOL4 semantics allows us to establish machine-checkable proofs regarding the semantics, properties of P4 programs, and soundness of analysis tools.
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SESSION: Monitoring and Applications
Causal Network Telemetry

Yunhe Liu (Cornell University), Nate Foster (Cornell University), Fred B. Schneider (Cornell University)
Current approaches to network observability rely on techniques like active probing, packet sampling, and path-level telemetry, which only provide a partial view. This paper presents causal telemetry, a new model that adapts ideas from distributed systems to the network setting. Causal telemetry captures causal relationships between events, including those that take place on physically separated devices. We motivate causal telemetry through examples, we show how it can be used to diagnose anomalies and faults, and we present algorithms for constructing the needed causal graphs from network executions. We develop a P4-based prototype implementation, CoCaTel, and discuss a case study that uses causal telemetry to detect Priority-Based Flow Control (PFC) deadlocks.
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Innovative network monitoring techniques through In-band Inter Packet Gap Telemetry (IPGNET)
Francisco Germano Vogt (University of Campinas), Fabricio Rodriguez (University of Campinas), Christian Esteve Rothenberg (University of Campinas), Gergely Pongrácz (Ericsson Research)
Network monitoring is a fundamental task for proper network troubleshooting and performance management. Recently, in-band Network Telemetry (INT) has been demonstrated as a powerful and efficient network monitoring framework. Using INT, network information hop-by-hop can be collected directly from the data plane by gathering this information in the production traffic. However, INT data collection is limited by available packet size and processing overhead, making it critical to choose what data to collect and when to collect it. In this demo, we propose the In-band Inter Packet Gap Network Telemetry (IPGNET) per-hop monitoring. We argue that by monitoring the IPG hop-by-hop, it is possible to correlate the data and identify: (i) Network problems like congestion and delays, finding their root cause, and (ii) Microbursts and their contributing flows. Our preliminary results show that IPGNET can detect microbursts on multiple queues and report all the contributing flows with high efficiency in terms of control/data plane overhead.

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Sketch-based Entropy Estimation: a Tabular Interpolation Approach Using P4 (Short Paper)
Yu-Kuen Lai (Chung-Yuan Christian University), Se-Young Yu (International Center for Advanced Internet Research), Iek-Seng Chan (Chung-Yuan Christian University), Bo-Hsun Huang (Chung-Yuan Christian University), Che-Hao Chang (National Taiwan University), Jim Hao Chen (International Center for Advanced Internet Research), Joe Mambretti (International Center for Advanced Internet Research)
This work presents the implementation of a tabular interpolation approach to estimate empirical Shannon entropy on programmable data plane ASICs using P4. The technique transforms the complex computations of the random projection into fast lookup over pre-computed tables in the match-action pipeline. Likewise, the interpolation heuristic further reduces the table size substantially. Thus, more tables can be accommodated, achieving higher estimation accuracy. Simulations based on real-world network traffic traces are performed to evaluate the estimation accuracy. The scheme is deployed in a Barefoot Tofino2 switch connected to the International Center for Advanced Internet Research (iCAIR) national testbed. The system can estimate the entropy of network traffic accurately at 400 Gbps throughput.
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In-network Angle Approximation for Supporting Adaptive Beamforming
Hiba Mallouhi (ELTE Eötvös Loránd University, Budapest, Hungary), Jaspreet Kaur (University of Glasgow), Hasan Tahir Abbas (University of Glasgow), Sándor Laki (ELTE Eötvös Loránd University, Budapest, Hungary)
Beamforming is now an integral feature of modern wireless communication systems and its implementation calls for an accurate beam alignment by estimating the direction of signal arrival. However, this estimation is computationally complex, especially in a dynamic environment where a user is constantly on the move. In this paper, we propose a user-assisted in-network method to optimally approximate the angle of arrival by segmenting the cell area into an exponentially binned grid and make use of the advantages offered by programmable data planes and their match-action table (MAT) logic. The proposed method is implemented in P4 and runs on a Tofino ASIC. Our evaluation proves a theoretical bound on the absolute error of the proposed MAT-based angle approximation and shows that it is in accordance with the empirical error distributions.

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Distributed DNN Serving in the Network Data Plane
Kamran Razavi (Technical University of Darmstadt), George Karlos (Vrije Universiteit Amsterdam), Vinod Nigade (Vrije Universiteit Amsterdam), Max Mülhäuser (Technische Universität Darmstadt), Lin Wang (Technische Universität Darmstadt, Vrije Universiteit Amsterdam)
There is a great interest in utilizing P4 for in-network computing along with programmable data planes. This use is emerging as a new network paradigm that can not just reduce the complexity but the delay as well. Beamforming is now an integral feature of modern wireless communication systems and its implementation calls for an accurate beam alignment by estimating the direction of signal arrival. However, this estimation is computationally complex, especially in a dynamic environment where a user is constantly on the move.
In this paper, we propose a user-assisted in-network method to optimally approximate the angle of arrival by segmenting the cell area into an exponentially binned grid and make use of the advantages offered by programmable data planes and their match-action table (MAT) logic. The method expects location messages periodically reported by user equipment, processes them in the network and reconfigures the base station antennas accordingly, implementing user-assisted in-network beam control. The proposed method is implemented in P4 and runs on a Tofino ASIC.
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Organizer Co-Chairs

Gianni Antichi, Queen Mary University of London
Fernando Ramos, University of Lisbon

TPC Co-Chairs

Marco Chiesa, KTH Royal Institute of Technology
Shir Landau Feibish, Open University of Israel

Publicity Chair

Marco Savi, University of Milano-Bicocca

Program Committee

Alan Zaoxing Liu (Boston University)
Amedeo Sapio (Intel)
Ben Pfaff (VMware)
Daehyeok Kim (Microsoft Research)
Damu Ding (University of Oxford)
Gábor Rétvári (Budapest University of Technology and Economics)
Hyojoon Kim (Princeton University)
Mihai Budiu (VMware Research)
Mina Tahmasbi Arashloo (University of Waterloo)
Muhammad Shahbaz (Purdue University)
Ori Rottenstreich (Technion)
Roberto Bifulco (NEC Laboratories Europe)
Salvatore Signorello (University of Lisbon)
Sándor Laki (Eötvös Loránd University)
Simone Ferlin (Red Hat, Karlstad university)

2023 APRICOT APNIC 55
2023-02-20 14:30 - 2023-03-02 16:00
March 1st | 2:30 – 4:00 pm | Visayas Ballroom
View Video (1:29)
Check out this insightful tutorial, “P4 Programming Protocol-Independent Packet Processor”, now on-demand, by ONF Ambassador and National University of Singapore (NAS) Research Fellow, Aris Cahyadi Risdianto. In his talk he provides an introduction to P4 and data plane programmability using the P4 programming language, concluding with a demo on programming a switch using P4.

FOSSASIA Summit 2023
2023-04-14 11:15
April 14th | 11:15 am SGT
Aris Cahyadi Risdianto, ONF Ambassador and Research Fellow, National University of Singapore, presented “Develop and Verify Networking Program with P4 and Mininet,” at FOSSASIA Summit 2023.
Abstract: P4 (programming protocol-independent packet processors) is a special language to define how the network packet forwarding process is built independently from the underlying hardware. It can be used to dynamically reconfigure the forwarding process on the different target hardware, such as ASIC, FPGA, or SmartNIC. Users can write complete networking programs that includes in-band telemetry/measurement, traffic load-balancing, anti-DDoS, packet broker, and offload protocols. The program can be tested using widely available network emulator, called Mininet, so that the behavior of packet forwarding can be verified before it is deployed in the real target hardware. In this presentation, we will quickly go through on how the P4 program looks like, how to compile, and how it is verified using Mininet emulator software.

2023 P4 Workshop
2023-04-24 08:00 - 2023-04-25 08:00
The P4 Workshop is an opportunity for the P4 ecosystem to share knowledge and experiences with the broader community and to facilitate collaboration. The workshop incorporates insights and perspectives from the P4 community across the following key areas:

P4 language
P4 targets
P4 tool chain
P4 use cases & applications
Control plane or network OS for P4 targets
Extensions to P4
Cross-cutting work between P4 and related systems such as eBPF and service meshes.

View individual videos and slides below! Or, view YouTube playlist.
Keynotes

Title
Video
Slides

Welcome & State of P4
Mina Tahmasbi Arashloo, Program Chair, University of Waterloo
Andy Fingerhut, Principal Engineer, Intel

Fireside Chat with Nick McKeown
Nick McKeown, P4 Co-founder & Evangelist
Larry Peterson, Chief Scientist, ONF

Developing Real World Applications Using P4-Based Architecture
Krishna Doddapaneni, Corporate Vice President, AMD Pensando

P4 HAL for Network Virtualization
Parveen Patel, Google Cloud, Senior Director Engineering, Google Cloud

The Power of Fully-Specified Data Planes
Rob Sherwood, Chief Technology Officer, NEX Cloud Networking Group, Intel

From Programmability to Fungibility
Ang Chen, Assistant Professor Computer Science, Rice University

Can SmartNICs Help Accelerate Distributed Systems?
Arvind Krishnamurthy, Short-Dooley Professor, Paul G. Allen School of Computer Science & Engineering, University of Washington

In-Depth Talks

Title
Video

Slides

Escaping Babel: The Flow Must Go On
Victor Rios, Google

OpenConfig Co-Existence with P4 Using TDI
James Choi, Cloud SW Architect, Intel

Formalizing and Extending P4’s Type System
Parisa Ataei, Postdoc, Cornell University

Effective DGA Family Classification Using a Hybrid Shallow and Deep Packet Inspection Technique on P4 Programmable Switches
Ali AlSabeh, University of South Carolina

Segment Routing Proxy Device implemented Using P4 on FPGA with Zero CPU Overhead
Miroslaw Walukiewicz, Intel

Hardware Offload Driver with P4-TC
Anjali Singhai Jain, Network Architect, Intel
Namrata Limaye, Intel

P4TC: Linux Kernel P4 implementation Approaches and Evaluation
Deb Chatterjee, Intel
Jamal Hadi Salim, Mojatatu Networks

Augmenting P4-DPDK Software Pipelines with Accelerators: the IPsec Use Case
Andy Fingerhut, Intel

Lightning Talks

Title
Video

Slides

Intent-based Platform Leverages Programmable Networking for Optimizing Edge
Dave Duggal, Founder/CEO, EnterpriseWeb
William Malyk, Chief System Architect, EnterpriseWeb

A Language Engineering Approach to Support the P4 Coding Ecosystem
Alexandre Lachance, Graduate Student, McMaster University

Enhancing Blockage Detection and Handover on 60 GHz Networks with P4 Programmable Data Planes
Ali AlSabeh, Computer Science PhD Student, University of South Carolina

P4MS: Leveraging Passive Measurements from P4 Switches to Dynamically Modify a Router’s Buffer Size
Jose Gomez, Graduate Assistant, University of South Carolina

P4 Working Group Update

Title
Video

Slides

What’s New in P4-16
Mihai Budiu, P4 Language Design Working Group Co-Chair

P4.org Architecture Work Group
Mario Baldi, P4 Architecture Working Group Co-Chair
Andy Fingerhut, P4 Architecture Working Group Co-Chair

P4 API Working Group Annual Wrap-up
Chris Sommers, API Working Group Co-Chair
Steffen Smolka, API Working Group Co-Chair

Demos

Title
Video

Slides

A Language Engineering Approach to Support the P4 Coding Ecosystem
Alexandre Lachance, Graduate Student, McMaster University

Demo to Offload Networking Pipeline on Intel IPU E2000 Using P4 Control Plane
Nupur Uttarwar, Cloud Software Engineer, Intel
Namrata Limaye, Senior Engineering Manager, Cloud Software, Intel

Enabling P4 hands-on Training Using Hardware Switches in a Cloud System at the University of South Carolina
Jose Gomez, Graduate Assistant, University of South Carolina

Enhancing Blockage Detection andHandover on 60 GHz Networks with P4 Programmable Data Planes
Ali AlSabeh, Research Assistant, University of South Carolina

Posters

Title
Details

A Testbench for Testing Programmable Traffic Managers in a Software Environment
Bill Pontikakis, Research Associate, Polytechnique Montreal

Casual Network Telemetry
Yunhe Liu, Research Assistant, Cornell University

Enhancing Blockage Detection and Handover on 60 GHz Networks with P4 Programmable Data Planes
Ali AlSabeh, Research Assistant, University of South Carolina

Extending the P4 Language to Facilitate the Use of Stateful Constructs
Jorg Ehmer, Polytechnique Montreal

Intent-based Platform Leverages Programmable Networking for Optimizing Edge
Dave Duggal, Founder/CEO, EnterpriseWeb
William Malyk, Chief System Architect, EnterpriseWeb

Euro P4 2023
2023-12-08 08:00
EuroP4 2023 took place December 8th in conjunction with ACM CoNEXT 2023 in Paris (France). This event brought together networking researchers and practitioners to discuss cutting-edge, P4-enabled research and P4-based technology. The workshop provided a venue for presenting and discussing research and projects related to P4, as well as for more broadly discussing the needs of this research community. The workshop aimed to forge new connections between researchers who already work with P4, introduce more networking researchers to the P4 community, and seed future top-tier publications, innovation and contributions to this community.
View proceedings from the 2023 EuroP4 Workshop

Session 1: P4 Networking

LANTERN: Layered Adaptive Network Telemetry Collection for Programmable Data Planes
Kaiyu Hou (Alibaba Cloud), Dhiraj Saharia (Georgetown University), Vinod Yegneswaran (SRI International), Phil Porras (SRI International)

Abstract:
Managing next-generation enterprise networks requires collecting and analyzing enormous volumes (tens of Tbps) of network traffic data in real time to detect potential anomalies, classify attacks, identify root causes, and rapidly deploy effective mitigations. Conducting robust and scalable analysis on such traffic volumes is a daunting ”haystack” problem that demands intelligent strategies to winnow traffic to extract and pinpoint ”needles” of interest. Recent advances in software-defined networking and programmable dataplanes, that enable dynamic reconfiguration of switching hardware to adapt to changing traffic conditions, provide a foundational building block. However, they lack the resources and programming primitives for complex computational models.
Toward that end, we present LANTERN, a layered and adaptive network telemetry system that facilitates joint collection and analysis of network traffic at multiple resolutions in coordination with the controller. Our design offloads complex machine-learning analysis to the controller, while still enabling proactive telemetry refinement and reactive mitigation triggers at the data-plane level. We evaluate our layered approach by replaying a labeled CIC-IDS attack dataset through both software and hardware P4 switches. LANTERN is able to detect most anomalies, accurately classify them, and introduces negligible switching overhead (1% latency).
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Per Priority Data Rate Measurement in Data Plane
Habib Mostafaei (Eindhoven University of Technology), Georgios Smaragdakis (Delft University of Technology)
Abstract:
Many applications, such as video streaming, congestion control, and server selection, can benefit when the data rate of different priority groups between two endpoints is accurately estimated over the end-to-end path. With the introduction of programmable networks, e.g., P4, it is now possible to offload the measurements to the data plane of intermediate devices. Recently, tools have been developed to react to changes in available bandwidth, but a tool to accurately estimate end-to-end per-priority data rates needs to be added. This motivates us to design and implement a new end-to-end and per-priority data rate estimation tool, PrioMeter. PrioMeter can accurately report the data rate per priority group of flows in programmable networks using high-precision timestamps for arbitrary traffic scales. PrioMeter leverages two primitives: quantization and truncation, to achieve its goals. We implement PrioMeter in P4 and test it on BMv2 switches, and our preliminary results using NS3 simulations show that it can accurately estimate the data rate of different priority flows with minimal overhead.
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Cryptographic Path Validation for SCION in P4
Lars-Christian Schulz (OVGU Magdeburg), Robin Wehner (OVGU Magdeburg), David Hausheer (OVGU Magdeburg)
Abstract:
SCION has been proposed as a new Internet architecture addressing security and scalability shortcomings in the current Internet. Multiple real-world deployments of SCION exist already, nevertheless few hardware implementations of SCION routers are available.
In this paper, we implement a SCION border router on a programmable 12.8 Tbit/s Intel Tofino 2 switch. Our router utilizes the multiple separately programmable packet pipelines of Tofino 2 in order to compute SCION’s AES-CMAC-based hop authenticators in general-purpose P4 without assistance from specialized hardware.
Using three out of four available pipelines, we achieve 394.7 Gbit/s throughput per port on 8 ports for a total of 3.16 Tbit/s capacity. Using only two pipelines we still achieve line rate throughput on 4 ports for a total of 1.58 Tbit/s capacity. To our knowledge there is no other SCION router including the AES-CMAC validation that offers a comparable performance.
Read Paper | View Slides

Session 2 – P4 Control & Targets

Introducing P4TC – A P4 Implementation on Linux Kernel using Traffic Control
Jamal Hadi Salim (Mojatatu Networks), Deb Chatterjee (Intel Corporation), Victor Nogueira (Mojatatu Networks), Pedro Tammela (Mojatatu Networks), Tomasz Osinski (Intel Corporation), Evangelos Haleplidis (Mojatatu Networks), Balachandher Sambasivam (Intel Corporation), Usha Gupta (Intel Corporation), Komal Jain (Intel Corporation), Sosutha Sethuramapandian (Intel Corporation)
Abstract:
The networking industry is at an inflection point with ever increasing network link capacities coupled with the presence of programmable hardware ASICs. These set of circumstances call out for a robust approach to hardware and software co-existence for network programmability.
P4TC is a P4 Linux kernel-native implementation on top of the Linux Traffic Control (TC) infrastructure that provides a vendor-neutral, kernel-independent and architecture-independent interface for Match-Action packet processing compatible with the P4 specification. P4TC facilitates both a hardware datapath and a functionally equivalent kernel eBPF-assisted software datapath making it ideal to deal with both high speed links and programmable hardware.
In this paper, we describe the goals and motivation of P4TC, the design and architecture as well as illustrate the different concepts of the P4TC infrastructure via an example of a simple L2 switch.
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NAP: Programming data planes with Approximate Data Structures
Mengying Pan (Princeton University), Hyojoon Kim (University of Virginia), Jennifer Rexford (Princeton University), David Walker (Princeton University)
Abstract:
Many applications that run on programmable data planes rely on approximate data structures, due to insufficient in-network memory. However, programming with approximate data structures is challenging because it requires (1) expertise in streaming algorithms to select the data structures that best match an application’s requirements, (2) meticulous configuration to minimize approximation error while fitting within the hardware constraints, and (3) proficiency in the low-level P4 language. To address these issues, we propose NAP, a high-level network programming language. The core of NAP is the versatile approximate dictionary abstraction that captures a wide range of compact data structures, while allowing programmers to simply specify the kinds of error an application can tolerate. We demonstrate the language’s expressiveness, conciseness, and efficiency through a variety of network applications, each compiling to P4 for the Intel Tofino in less than a second and featuring 25X–50X fewer lines of code compared to the P4 output. We evaluate an approximate stateful firewall written in NAP with real campus traffic, achieving performance consistent with the predicted accuracy.
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P4EAD: Securing the In-band Control Channels on Commodity Programmable Switches
Archit Bhatnagar (Birla Institute of Technology & Science, Pilani), Xin Zhe Khooi (National University of Singapore), Cha Hwan Song (National University of Singapore), Mun Choon Chan (National University of Singapore)
Abstract:
Conventionally, the control channel on network switches has always been out-of-band. With the emergence of high-performance systems built upon programmable switches, the out-of-band control channel has become the bottleneck. Thus, there is an emerging trend of implementing the control channel in the data path (i.e., in-band) on programmable switches to achieve high throughput and low-latency control actions. However, the use of in-band control channels comes with the risk of security vulnerabilities that have not been explored in prior literature. In this paper, we present P4EAD, a cryptographic primitive to secure the in-band control channels on programmable switches entirely in the data plane. This ensures the integrity, authenticity, and confidentiality of in-band control messages. We conduct micro-benchmarks on P4EAD and demonstrate its integration with an existing high-performance in-band control framework, showcasing minimal performance impact when securing the control channel.
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Posters and Demos Session
Poster: High-Speed Per-Packet Checksums on the Intel Tofino
David Grölle (OVGU Magdeburg), Lars-Christian Schulz (OVGU Magdeburg), Robin Wehner (OVGU Magdeburg), David Hausheer (OVGU Magdeburg)
Abstract:
Path-aware networking has introduced new possibilities to monitor and control network access and solved a multitude of modern-day Internet security issues. Being able to authorize usage of specific paths enables network operators to offer high-quality services to customers requiring highly reliable network access.
Currently, securing a network path or an end host is only possible by using high-level solutions like VPNs. With EPIC-HP (Every Packet Is Checked – Hidden Path), it has been shown that it is possible to move this functionality down into the network itself. EPIC-HP extends the path-aware Internet architecture SCION by offering per-packet checksums, adding authentication to network traffic. This is used to combat DoS attacks on the network’s end hosts and give high-priority access to specific end users. In this paper, we show that it is possible to implement the functionality of EPIC-HP along with SCION on the Intel Tofino 2 ASIC. EPIC-HP requires AES-based MAC verification with per-path keys in the data plane. By using the multi-pipeline structure of the Tofino, we implemented the required AES and AES-CMAC cryptography using three pipes of the switch’s total four independent pipes.
The throughput we achieve is an order of magnitude above the data rates previously achieved for EPIC-HP and is a significant step towards a more secure Internet.
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Poster: P4DME: DNS Threat Mitigation with P4 In-Network Machine Learning Offload
Juan Vanerio (University of Vienna), Csaba Györgyi (University of Vienna), Stefan Schmid (TU Berlin, Fraunhofer SIT)
Abstract:
The ever-evolving cybersecurity landscape demands innovative solutions to safeguard critical network infrastructure such as the Domain Name System (DNS). This paper presents P4DME, a novel approach that harnesses the potential of Machine Learning (ML) in conjunction with P4 programmable switches to tackle DNS threats efficiently. P4DME’s primary benefit lies in offloading filtering from resource-intensive ML processing tasks on dedicated servers. This offloading boosts the overall traffic throughput that can be inspected or achieves the same throughput with reduced resource consumption while preserving the servers’ capabilities for high-performance threat identification. This work uses P4-based in-network elements to handle crucial DNS threats, dynamic white- and blacklisting, and an online popularity-based anomaly detection heuristic. The latter serves as a trigger for dedicated ML-based inspection. Furthermore, we introduce in-network mitigation filters updated through the control plane to provide adaptable and responsive threat mitigation. Preliminary simulation results show more than 99.9% offload ratio at 5% increased False Negative Ratio.
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Poster: Maintaining Sets With Deletions in the Data Plane
Jonathan Diamant (The Open University of Israel), Shir Landau Feibish (The Open University of Israel)
Abstract:
Sets are one of the most fundamental data types in Computer Science, and data structures used to maintain sets are used in many algorithms. These structures normally support three basic operations: insertion, look-up (i.e. set-membership query), and deletion. The most common set-membership data structure used in the data plane is the Bloom Filter (BF). While BFs are relatively easy to adapt to the data plane, they offer a limited set-membership functionality as they do not support deletions. If deletions are required, a Counting Bloom Filter (CBF) (which maintains counters instead of bits) may be used. Yet, if a key was inserted multiple times, multiple deletions would be needed to completely remove the key from the structure. We present MEM-D, a fast and lightweight set-membership data structure for the data plane, which supports all three operations: look-up, insertion, and deletion. MEM-D supports the uniqueness property, meaning that a key would be removed with a single deletion operation even if it was inserted multiple times. MEM-D provides a false positive (FP) error rate similar to the rate of the standard BF and additionally may incur a small false negative (FN) error. We have implemented MEM-D on a hardware Tofino target using P4. To the best of our knowledge, MEM-D is the first data structure for set-membership in the data plane, which supports deletion.
Read Paper

Poster: Adaptive In-Network Inference using Early-Exits
Heewon Kim (Korea University), Seongyeon Yoon (Korea University), Sangheon Pack (Korea University)
Abstract:
In-network (or on-path) inference over programmable data planes allows fast and low-overhead inference in deep neural networks. In this work, we propose an adaptive approach to strike the balance between accuracy and processing cost. To be specific, the confidence score is evaluated at the end of each layer, and an early exit is triggered if the confidence score is sufficiently high. We implement this early-exit scheme over BMv2 software switches and the results demonstrate that the proposed scheme successfully controls the trade-off by making use of the confidence score.
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Demo: Enabling DNN-Based Inference in the Network Data Plane
Siddhartha (AMD), Justin Tan (AMD & NUS), Rajesh Bansal (AMD), Chee Chung Chan (AMD), Yuta Tokusashi (AMD), Yew Kwan Chong (AMD), Haris Javaid (AMD), Mario Baldi (AMD)
Abstract:
Advancements in programmable packet processing technologies have fostered innovation across a range of networking applications. Integration of deep neural networks (DNN) in the network data plane, however, has remained largely unaddressed due to the high compute requirements of the underlying algebraic kernels. In this paper, we show how P4 packet processing pipelines can be augmented with DNN inference engines on devices readily available in the market today. We share a network security case study, where we train a DNN-based anomaly detector that classifies active traffic flows as either malicious or benign using per-packet inference. Our implementation runs on an AMD AlveotextsuperscriptTM U250 FPGA accelerator card, and is capable of servicing network traffic of up to approx~98~Mpps on 100~GbpE links.
Read Paper

Workshop General Chairs
Fernando Ramos, University of Lisbon
Muhammad Shahbaz, Purdue University
Program Chairs
Vladimir Gurevich, P4ica
Salvatore Signorello, Telefonica Research, Spain
Publicity Chairs
Denise Barton, ONF
Sandor Laki, Eötvös Loránd University
Program Committee
Alan Lo, NVIDIA
Alan Zaoxing Liu, University of Maryland
Andy Fingerhut, Intel
Anirudh Sivaraman, New York University
Christian Esteve Rothenberg, University of Campinas
Daehyeok Kim, University of Texas at Austin
Davide Sanvito, NEC Labs
Ennan Zhai, Alibaba Cloud
Gianni Antichi, Politecnico di Milano & Queen Mary University of London
Jiarong Xing, Rice University
Mario Baldi, AMD & Politecnico di Torino
Nate Foster, Cornell University
Nik Sultana, Illinois Institute of Technology
Robert Soulé, Yale University
Shir Landau Feibish – The Open University of Israel

P4 Open Source Developer Days: P4 Traffic Generator and Analyzer
2024-04-02 08:00
April 2nd 2024
In case you missed it, you can now watch the recording of the recent P4 Developer Days Talk by Steffen Lindner (University of Tuebingen) on the P4TG traffic generator and analyzer.
“We present P4TG, an open-source P4-based traffic generator (TG) which runs on the programmable Intel Tofino ASIC. In generation mode, P4TG is capable of generating traffic up to 1 Tb/s split across 10x 100 Gb/s ports. Thereby it measures rates directly in the data plane. Generated traffic may be fed back from the output to the input ports, possibly through other equipment, to record packet loss, packet reordering, inter-arrival times (IATs) and sampled round trip times (RTTs). Further, it supports VLAN, QinQ, and MPLS encapsulation. In analysis mode, P4TG measures rates on the input ports and IATs, and forwards traffic through its output ports. Existing software or P4-based traffic generators either lack the required accuracy, do not support high data rates, or do not provide sufficiently integrated measurement capabilities.”

ONE Summit 2024: P4-Based Automated Reasoning
2024-04-29 08:00 - 2024-05-01 08:00
Check out the video and slides by P4 TST member Steffen Smolka, “P4-based Automated Reasoning” which was featured at The Linux Foundation’s One Summit 2024. In his talk he discusses how P4 is now being used as a specification language for network programmable and non-programmable pipelines. He discusses how Google and others have been leveraging such machine-readable, unambiguous, vendor-agnostic specifications of their switches to increase network reliability and development as well as allow the SDN controller to interoperate seamlessly with switches form different vendors.

View Video
Review Slides

2024 P4 GSoC Projects - Webinar
2024-09-05 09:00
Thursday, September 5, 2024
9:00am Pacific
View Video
Learn about the four exciting projects hosted by the P4 Language Organization as part of Google‘s Summer of Code (GSoC) 2024. Each of the project contributors present their projects followed by a short discussion.
P4 Projects in GSoC

View Project Details
Improving the documentation of the P4 Compiler
Contributor: Adarsh Rawat, Graphic Era Deemed to be University
Mentors: Fabian Ruffy, Davide Scano
Building a Formatter for the P4 Language
Contributor: Nitish Kumar, Indian Institute of Technology Kharagpur
Mentors: Bili Dong, Fabian Ruffy
Introducing PNA support to BMv2
Contributor: Rupesh Chiluka, University of Hyderabad (UoH)
Mentors: Hari Thantry, Debobroto Das Robin
P4-Enabled Container Migration in Kubernetes
Contributor – Stanislav Korosin, Technische Universität Berlin
Mentors: Davide Scano, Radostin Stoyanov

2024 P4 Workshop
2024-10-03 08:00
The 2024 P4 Workshop took place October 3rd, and was hosted and sponsored by Google. This in-person event took place at Google’s Moffett Park Campus in Sunnyvale, California and offered an opportunity for the P4 ecosystem to share knowledge and experiences with the broader community and to facilitate collaboration.
View individual videos and slides on-demand from the event below! Or, view YouTube Playlist.
Invited Talks

Title
Video
Slides

Welcome, State of P4 & 2024 Distinguished Contributor Award
Andy Fingerhut, Principal Engineer, Intel

Keynote – Navigating Internet Research with P4: Solutions for Performance and Security
Maria Apostolaki, Assistant Professor of Electrical and Computer Engineering, Princeton University

Fireside Chat with Martin Casado
Martin Casado, General Partner, Andreessen Horowitz
Nate Foster, Professor Computer Science, Cornell University

P4 on Hardware: The Future
Konstantin Weitz, Staff Software Engineer, Google (Moderator)
Vipin Jain, Sr Fellow Engineer, AMD
Anjali Singhai Jain, Network Architect, Intel

In-Depth Talks

Title
Video

Slides

Past, Present and Future of P4
Deb Chatterjee, Sr Director Software Engineering, Intel

Compiler-assisted Kernel-based P4 Pipeline Offloading Using Intel IPU
Deb Chatterjee, Sr Director Software Engineering, Intel
Neha Singh, Staff Software Engineer, Intel

Towards the Performant P4C
Anton Korobeynikov, Principal Software Engineer, Compiler Development, Access Softek Toolchains

Supporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme
Bill Pontikakis, Sr Research Associate, Polytechnique Montréal
François-Raymond Boyer, Professeur, Polytechnique Montréal

SONiC DASH on Intel IPU2100
Shweta Shrivastava, Cloud Software Engineer, Intel
Namrata Limaye, Director Software Engineering, Intel

Internals of the Intel Tofino Compiler
Glen Gibb, Compiler Engineer, Intel

P4-SpecTec – Mechanized Language Definition for P4
Jaehyun Lee, Student, KAIST

Centralized Telemetry and Security Enforcement Using SONiC and P4
Shekher Bulusu, Sr Manager Software Engineering, GEICO
Pawan Ravi, Sr Staff Engineer, GEICO
James Choi, Sr Engineering Manager, GEICO

Modeling Hardware Blocks of Network ASICs using P4
Jean Tourrilhes, Researcher, HPE

In-Memory Key-Value Store Live Migration with NetMigrate
Zeying Zhu, PhD Student, University of Maryland

P4-Based Automated Reasoning (P4-BAR) for the (Networking) Masses!
Steffen Smolka, Staff Software Engineer, Google
Jonathan DiLorenzo, Software Engineer, Google

Scaling P4-Based Automated Reasoning (Performance and Coverage)
Ali Kheradmand, Senior Software Engineer, Google
Meghana Sistla, PhD Student, University of Texas at Austin

P4HIR: Toward Bridging P4C with MLIR
Bili Dong, Software Engineer, Google

Demos

Title

Abstract

SONiC DASH on Intel IPU2100
Namrata Limaye, Director Software Engineering, Intel

Data Center Routing GEICO SDN Controller and GEICO SONiC Using P4
Sunil Kumar Rawookar, Staff Engineer, GEICO Tech

Offload NAT and Routing onto Intel IPU Using P4-TC
Neha Singh, Staff Software Engineer, Intel

P4 IDE: An Integrated Development Environment for P4-based Data Plane Development
Namrata Limaye, Director Software Engineer, Intel

P4Docker: Simplifying P4 Switch Testbeds with Docker Integration
Lucas Trombeta, PhD Candidate, Federal University of ABC (UFABC)

Supporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme
Bill Pontikakis, Sr Research Associate, Polytechnique Montréal
François-Raymond Boyer, Professeur, Polytechnique Montréal

Poster

Title
Abstract

Babel: The Tower So Far
Victor Rios, Software Engineer, Google

General Chair – Nate Foster
Program Co-Chairs – Andy Fingerhut, Muhammad Shahbaz
Program Committee
– Jehandad Khan, AMD
– Ori Rottenstreich, Technion
– Vishal Shrivastav, Purdue University
– Gianni Antichi, Politecnico di Milano and Queen Mary University of London
– Ben Pfaff, Feldera
– Ajay Lotan Thakur, Intel Corp
– Victor Liu, University of Michigan
– Vladimir Gurevich, P4ica
– Tushar Swamy, unaffiliated
– Yiming Qiu, University of Michigan
– Amedeo Sapio, Amazon Web Services
– Lavanya Jose, Google

Japan P4 Users Group
2024-10-25 08:00
The 2024 Japan P4 Users Group was hosted as a hybrid in-person and online event and included P4-related presentations and exhibits. View the agenda and resources. Talks were presented in Japanese and video can be accessed here.

P4 Developer Days - P4 in SDN-based Attack Detection and AI-driven Security Mechanisms
2025-05-06 08:00
May 6, 2025 | 8:00am Pacific
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View Slides
Abstract
Software-Defined Networking (SDN) is a promising network architecture that offers greater flexibility and scalability compared to traditional network infrastructures. This flexibility arises from the separation of the data plane from the control plane, which enables the use of general-purpose devices, commonly referred to as “dumb devices” in SDN. While this separation enhances network management and administration, it also imposes processing limitations, leading to increased overhead on the controller. This is precisely where P4, a domain-specific programming language for packet processing, becomes highly beneficial.
In the field of network security, particularly in attack detection, researchers have proposed various innovative methods. P4 can play a crucial role in advancing these solutions by leveraging a programmable data plane to offload processing tasks from the controller, thereby achieving a more balanced distribution of computational load between the data and control planes. One of the most critical areas of application in this regard is the detection and mitigation of Distributed Denial-of-Service (DDoS) attacks.
Additionally, there has been a significant rise in AI-based security solutions, with machine learning (ML) being a prominent subfield. ML enables the development of custom AI agents tailored for specific tasks, requiring the extraction of relevant features for training purposes. However, without a programmable data plane, this approach is impractical in both SDN and traditional networks. With P4, however, such implementations become feasible, opening new possibilities for AI-driven network security solutions.
In this webinar, we will explore the use cases of P4 in SDN-based attack detection and AI-driven security mechanisms, highlighting its potential to enhance modern network security strategies.
Speaker
Reza Fallahi Kapourchali holds an M.Sc. in Computer Networks from Bu-Ali Sina University, Hamedan, Iran. His research interests encompass a broad spectrum of critical areas, including computer network security, P4 technology, wireless networks, 5G networks, the Industrial Internet of Things (IIoT), and network Quality of Service (QoS). His commitment to advancing innovation and knowledge in these fields is evidenced by his published articles, which contribute to the development of secure and efficient network architectures.

P4 Developer Days - P4 on Silicom ThunderFjord SmartNIC
2025-05-29 08:00
P4 Developer Days webinar, “P4 on Silicom ThunderFjord SmartNIC”
Date: May 29, 2025
Time: 8:00am Pacific
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Abstract
The integration of P4 into the FPGA of the Silicom ThunderFjord SmartNIC brings unprecedented flexibility and programmability to modern networking. This presentation explores the capabilities of the ThunderFjord SmartNIC, highlighting how P4 enables dynamic packet processing directly on the hardware. We will delve into the architecture of the SmartNIC, its role in enhancing network performance, and the benefits of using P4 to implement custom protocols, traffic management, and network offload functions.
Speakers
Lars Munch , Senior Software Engineer, Silicom Denmark
Lars holds a Master’s degree in Computer Science from the Technical University of Denmark (DTU), with research experience in embedded systems. With over two decades of expertise, he has developed high-performance software solutions for SmartNICs, IoT devices, and embedded Linux platforms. Currently, Lars is a Senior Software Engineer at Silicom Denmark, where he is responsible for the design, development, and optimization of software solutions related to SmartNICs, playing a key role in delivering advanced networking technologies.
Eleftherios Kyriakakis, FPGA Developer, Silicom Denmark
Eleftherios holds a PhD from the Technical University of Denmark (DTU) with a research focus on “Time-predictable End-system Design for Real-Time Communication”. He specializes in FPGA and ASIC design, particularly in developing fault-tolerant and real-time systems. His most notable published works include the implementation of a fault-tolerant inter-chip Network-on-Chip (NoC) communication bridge on FPGAs, memory controllers with single-event upset (SEU) detection, and research on precise time protocol (PTP) and time-triggered networks. Currently, Eleftherios is working as an FPGA engineer at Silicom Denmark, where he is responsible for the design and development of proof-of-concept solutions for SmartNICs.

P4 Developer Days - Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern Smart NICs
2025-06-04 08:00
P4 Developer Days webinar, “Pipeline-Aware Sub-Traversal Caching for Modern Smart NICs”
Date: June 4, 2025
Time: 8:00am Pacific
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Abstract
The success of modern public/edge clouds hinges heavily on the performance of their end-host network stacks if they are to support the emerging and diverse tenants’ workloads (e.g., distributed training in the cloud to fast inference at the edge). Virtual Switches (vSwitches) are vital components of this stack, providing a unified interface to enforce high-level policies on incoming packets and route them to physical interfaces, containers, or virtual machines. As performance demands escalate, there has been a shift toward offloading vSwitch processing to SmartNICs to alleviate CPU load and improve efficiency. However, existing solutions struggle to handle the growing flow rule space within the NIC, leading to high miss rates and poor scalability. In this paper, we introduce Gigaflow, a novel caching system tailored for deployment on SmartNICs to accelerate vSwitch packet processing. Our core insight is that by harnessing the inherent pipeline-aware locality within programmable vSwitch pipelines—defining policies (e.g., L2, L3, and ACL) and their execution order (e.g., using P4 and OpenFlow)—we can create cache rules for shared segments (sub-traversals) within the pipeline, rather than caching entire flows. These shared segments can be reused across multiple flows, resulting in higher cache efficiency and greater rule-space coverage. Our evaluations—performed using Xilinx Alveo U250 data center accelerator running a Gigaflow pipeline written in P4—show that Gigaflow achieves up to a 51% improvement in cache hit rate (average 25% improvement) over traditional caching solutions (i.e., Megaflow), while capturing up to 450x more rule space within the limited memory of today’s SmartNICs—all while operating at line speed.
Publication Link : https://dl.acm.org/doi/10.1145/3676641.3716000
Speaker
Annus Zulfiqar is a PhD candidate at the University of Michigan with Professor Muhammad Shahbaz. His research focuses on designing next generation hardware/software abstractions and architectures for emerging data center networking applications. Currently, he is working on designing a scalable and efficient fast path for the Open vSwitch, which is a widely used software switch in modern data centers. He is also working on ML for Systems where he has contributed to automatic generation of optimized data plane ML models and the development of scalable decision trees for programmable switches.

P4 GSoC 2025 Kickoff Meeting
2025-06-11 08:00
Learn about the projects hosted by the P4 Project in Google Summer of Code (GSoC) 2025. Each project will be presented by the contributor.
Agenda

Introduction – Nate Foster
GSoC proposal presentation + discussion:

BMv2 With All Possible Output Packets – Xiyu Hao
P4Sim Control Plane Enhancement – Vineet Goel
P4MLIR: MLIR-based high-level IR for P4 compilers – Xiaomin Liu
Accelerating OVS with Gigaflow: A Smart Cache for SmartNICs – Advay Singh
SpliDT: Scaling Stateful Decision Tree Algorithms in P4 – Sankalp Jha

VIEW VIDEO
VIEW SLIDES

P4 Developer Days - P4-based AI Feature Extractor for Volumetric Firewall Use Cases
2025-07-09 08:00
Date: July 9, 2025Time 8:00am Pacific
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Abstract
Using volumetry data is a very important feature of many firewalls from major security vendors. The changing security landscape and a need for performance and flexibility drive the use of AI/ML engines working more efficiently. The presentation shows an example of the use of P4 language to prepare a training feature and an example of an inference engine using P4 as a feature extractor for the SYN-FLOOD attack detector. The P4, as a packet processing language, can be used to define the network traffic-based features for AI/ML processing. The AI/ML engines can be abstracted as P4 externs. The P4 defines what packet fields are of interest in AI/ML process. Such P4 engine implementation (based on hardware or software) can also prepare/preprocess the AI/ML engine input (for example, rate of some packets or counter selection). It can also prepare the packet-based response using AI/ML external outcome. The presentation provides an overview of some challenges, like a lack of standardized datasets and performance requirements.
Speaker
Mirek Walukiewicz is a Principal Engineer at Altera with more than 32 years of experience in networking technology. He is a Solution Architect actively working with customers on various P4 applications using FPGA-like security, packet scheduling, clock synchronization, and more. He drives P4 efforts inside Altera.

P4 Developer Days - Gateway Use Case Architecture for Network Applications
2025-08-06 08:00
Date: August 6, 2025Time: 8:00am Pacific
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Abstract
Network applications demand ever-increasing performance and flexibility. Mapping P4 programs directly to FPGA hardware offers a powerful solution, but the design process can be complex. This presentation demonstrates a new toolchain for efficiently mapping P4 programs to Altera FPGAs, significantly accelerating gateway applications. Presentation leads attendees through the complete flow, from high-level P4 specification down to a fully synthesized FPGA design using a practical gateway example. Attendees will learn how this toolchain leverages p4 language capabilities to map the user application into FPGA. This session is ideal for network architects and hardware engineers seeking to leverage the power of P4 and FPGA acceleration for next-generation network applications.
Speaker
Pavel Benacek is Technical Lead at Altera with more than 12 years of experience in networking technology from research and industry. He is mainly working on hardware/software co-designs and high-level synthesis topics. He holds the Ph.D. at the Czech Technical University in Prague where he was working on theory of P4 language mapping to RTL design that can be synthesized to FPGA.

P4 Developer Days - Detecting Stragglers in Programmable Data Plane
2025-08-20 09:00
Date: August 20, 2025Time 9:00am Pacific
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Abstract
Flow scheduling mechanisms in modern datacenters aim to reduce flow completion time (FCT). However, scheduling mechanisms that operate without prior knowledge, such as PIAS, or with imprecise flow information like QClimb, can inadvertently introduce stragglers–packets within a flow that experience significantly higher queueing delays than others. These stragglers can lead to prolonged FCT, undermining the goals of flow scheduling. In this talk, we present StragFlow, a data-plane tool for straggler detection. We implemented StragFlow in P4 using 740 lines of code. We evaluated StragFlow using real-world network traces and demonstrate that it can effectively detect stragglers across different scheduling schemes and various link conditions. Our results show that StragFlow can provide valuable insights into straggler distribution, helping operators diagnose and mitigate flow scheduling issues to improve overall network performance.
Speaker
Riz Maulana is a PhD Candidate within IRIS Cluster in the Department of Mathematics and Computer Science at Eindhoven University of Technology, The Netherlands. His research interest includes programmable data plane, probabilistic data structures, and network monitoring.

P4 Developer Days - Mechanizing the P4 Language Specification with P4-SpecTec
2025-09-10 16:00
Date: September 10th 4:00pm PST | September 11th – 8:00am KST
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Abstract
The P4 language has four main representations of its syntax and semantics: the official specification, formalizations, implementations, and a test suite. While the four representations are intended to consistently define the P4 language, they often diverge, as each is managed by different parties and evolves at a different pace. This lack of alignment complicates both specification evolution and compiler maintenance.

To address this challenge, we present P4-SpecTec, a mechanized specification infrastructure for the P4 language. Inspired by successful language mechanization frameworks such as Wasm-SpecTec for WebAssembly and ESMeta for JavaScript, P4-SpecTec introduces a formal, complete, and mechanized P4 language definition. From this single source of truth — the mechanized specification — we aim to generate multiple backends, such as a type checker, interpreter, test suite, and specification document, in a consistent and automated manner.
P4-SpecTec is an ongoing project, where we currently mechanized the P4 type system. Notably, our mechanized type system is executable. That is, the typing rules can be executed, acting as a P4 type checker. Our mechanized specification passes more than 97% of the applicable tests in the p4c test suite. This process already revealed inconsistencies and underspecified behaviors in both the P4 specification and its reference compiler. Based on the mechanized model, we further developed a negative test generation technique that automatically produces ill-typed P4 programs that trigger subtle and diverse ill-typed conditions in the P4 type system. This approach has uncovered 11 compiler bugs and 12 soundness issues in the p4c frontend.
This talk introduces the design of P4-SpecTec, current progress, and long-term vision for a more robust and consistent P4 language ecosystem.
Speaker
Jaehyun Lee is a graduate student in the Programming Language Research Group at KAIST, advised by Sukyoung Ryu. His research focuses on mechanizing programming language definitions to improve their reliability and precision. He leads the P4-SpecTec project, which is a mechanized specification infrastructure for P4. Previously, he contributed to the Wasm-SpecTec project, now part of the official WebAssembly specification authoring toolchain. As part of that effort, he co-authored the paper “Bringing the WebAssembly Standard Up to Speed with SpecTec”, presented at PLDI 2024. His goal is to make language specifications reliable and better aligned with the needs of the developer community.

2025 P4 GSoC Wrap-up
2025-09-17 08:00
Date: September 17, 2025
Time: 8:00am Pacific
The wrap-up session highlights results of the projects hosted by The P4 Language Consortium during Google Summer of Code (GSoC) 2025. In its second consecutive year of participation, we are pleased to share the results from each of the projects. During this session, contributors will present their work, share key outcomes, and participate in a live Q&A.
Official GSoC 2025 Profile: The P4 Language Consortium
VIEW VIDEO
Agenda

Opening – Bili Dong, Google
P4 GSoC project presentation + discussion:

BMv2 with All Possible Output Packets – Xiyu Hao, New York University
P4Sim Control Plane Enhancement – Vineet Goel, Indian Institure of Technology Roorkee
Accelerating OVS with Gigaflow: A Smart Cache for SmartNICs – Advay Singh, University of Michigan
SpliDT: Scaling Stateful Decision Tree Algorithms in P4 – Sankalp Jha, Ajay Kumar Garg Engineering College

P4 Developer Days - From Semantics to Software: Building a Verification Ecosystem for P4 using HOL4P4
2025-09-25 08:00
P4 Developer Days webinar, “From Semantics to Software: Building a Verification Ecosystem for P4 using HOL4P4”
Date: September 25, 2025
Time: 8:00am Pacific
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Abstract
We present a comprehensive formal verification ecosystem for the P4 network programming language, built upon HOL4P4, an abstract model of P4 execution embedded in the interactive theorem prover HOL4. The HOL4P4 formalization provides a semantics and a corresponding type system with formally verified progress, preservation, and type-soundness theorems. In addition, it has been validated using a test suite from the P4 reference implementation.
From this robust semantic foundation, we have developed multiple practical verification tools. Our proof-producing symbolic execution engine enables functional correctness verification of entire real-world P4 programs, with all results mechanically verified against the HOL4P4 semantics. Additionally, we present a formally verified P4 software switch that maintains correctness guarantees from source to binary by leveraging both HOL4P4 and the verified CakeML compiler. This switch integrates seamlessly with existing network testing frameworks like Mininet while demonstrating decent performance compared to existing similar solutions.

Together, these contributions demonstrate how rigorous formalization can serve as the foundation for a complete ecosystem of verification tools, bridging the gap between theoretical guarantees and practical network development while meeting the growing demand for formal assurances in critical network infrastructure.
Speaker
Didrik Lundberg combines academic research as a PhD candidate at KTH Royal Institute of Technology with practical engineering experience at Saab AB. He specializes in interactive theorem proving and formal verification, particularly for low-level and network-related systems. His current focus is developing tools based on the HOL4P4 formalization of P4.

P4 Developer Days - Enabling Portable and High-Performance SmartNIC Programs with Alkali
2025-10-01 09:00
Date: October 1, 2025
Time: 9:00am Pacific
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Abstract
Programming SmartNICs today is notoriously difficult. NICs from different vendors—or even different generations of the same vendor—exhibit significant variation in hardware parallelism, memory hierarchies, and interconnects. As a result, porting programs across NICs is labor-intensive and requires extensive manual refactoring to meet performance expectations on each target.
In this presentation, we will present the demo and design of Alkali, a SmartNIC compilation framework that enables developers to write target-independent programs, while the compiler automatically handles cross-NIC porting and performance tuning. Alkali achieves this by: (1) introducing a novel intermediate representation (IR) that supports building a reusable and extensible compiler across diverse NICs, and (2) developing an optimization algorithm that automatically transforms and parallelizes programs based on the target NIC’s hardware characteristics.
Alkali is built on the MLIR infrastructure and is fully open source (https://github.com/utnslab/Alkali). It currently supports four distinct NIC backends and continues to grow, including future support for P4 as part of an effort to make SmartNIC programming more portable and productive.
Speakers
Jiaxin Lin is an incoming assistant professor at Cornell University. She received her Ph.D. from UT Austin in the summer of 2025. Her research aims to design innovative software and hardware for accelerated data center networks. She has received the Google and Meta PhD Fellowships in Computer Networking and was selected as an MIT EECS Rising Star in 2024.

Zhiyuan Guo is a final-year PhD student at UC San Diego. His research focuses on co-designing datacenter systems and applications for resource disaggregation. He is actively extending the concept of disaggregation and cohesive design to various datacenter systems, including remote memory, networking accelerators, and machine learning infrastructure.

2025 P4 Workshop
2025-10-13 12:00 - 15:30
October 13th, Noon – 3:30pm (in-person) – San Jose Convention Center, Lower Level, Room LL21B
The P4 Workshop event is an opportunity for the P4 ecosystem to share knowledge, insights and experiences across the broader community and to facilitate collaboration. This year the workshop will be a hybrid event and feature both in-person and pre-recorded content. The in-person portion of the workshop will take place on October 13th in conjunction with the 2025 OCP Global Summit at the San Jose Convention Center in San Jose, California.
In addition, a P4 booth will be in the OCP Global Summit exhibit hall – make sure and stop by to talk with community members and learn about P4, how its used and how to participate. Don’t miss a demo – “Gigaflow: Pipeline-Aware Caching in Virtual Switches with P4”.
P4 Workshop Agenda (October 13th – noon – 3:30pm)

Welcome – Fernando Ramos
General Chair 2025 P4 Workshop
View Video | View Slides
KEYNOTE: Mina Tahmasbi Arashloo – “High-Level and Target-Agnostic Transport Programs”
Assistant Professor Canada Research Chair in Minimizing Human Error in Modern Networks Cheriton School of Computer Science, University of Waterloo
Abstract: Over the past two decades, programming abstractios for packet processing have gained widespread adoption. These abstractions enable network operators to specify packet processing logic in high-level, domain-specific languages that are independent of the underlying hardware architecture of packet processing nodes. This approach has unlocked numerous benefits, including compiler-driven generation of efficient low-level implementations, portability across diverse execution environments, and automated testing and verification. Most existing abstractions, however, primarily focus on L2/L3 packet processing. In this talk, we highlight the need for new programming abstractions that capture the complexities of network mechanisms essential for quality of service, specifically transport protocols.
View Video | View Slides
Victor Rios – “DVaaS Detective: The Case of the Failing Tests”
Software Engineer, Google
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Anand Sridharan – “Cisco Silicon One: Unifying Network Forwarding with P4 Programmability”
Distinguished Engineer, Cisco
View Video | View Slides
BREAK
Tom Herbert – “Unifying P4 with eBPF and DPDK via XDP2”
CEO, XDPnet
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Debashis Chatterjee – “New Dawn of P4”
Senior Director of Engineering, Intel
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Fabian Ruffy | Vladimir Gurevich – “XASM: A Foundation to Program the X2 with P4”
Software Architect | Customer Solutions Architect, XSight Labs
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KEYNOTE: Krishna Doddapaneni – “Using P4 NICs for Resilient Scale-out GPU Interconnect”
Corporate Vice President, AMD Pensando
Abstract: AI transports demand hardware-based solution for low latency, high throughput GPU interconnects. P4 seems a perfect match for demanding datapath transport enabled on programmable NIC for scale-out Ethernet fabrics. The industry is standardizing packet processing, memory transfers, message processing, reliability, multipathing, etc. over the last few years. And we are at the beginning of building and standardizing these solutions. As network components multiplies — from cables and NICs to switches and transceivers, failures become an inevitability. Chasing a myth of perfect reliability, a more practical approach is to design a programmable network that anticipates and handles these failures gracefully.

This talk discusses how AMD leverages the P4 to build a robust solution that overcomes network failures, implementing a multi-plane architecture and advanced failure-handling mechanisms. How P4 capabilities demonstrate network data plane programmability is a foundational requirement in today’s demanding and unforgiving AI environments.
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Andy Fingerhut – P4 Workshop Wrap-up
Principal Engineer, Cisco

P4 Workshop Pre-Recorded Talks

Eric Campbell – “When P4 Isn’t Enough: Specifying The Control Interface”
Postdoctoral Research Fellow, UT Austin
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Mehmet Emin Sahin – “High-Accuracy Updatable Bloom Filters for Robust Network Security in Programmable Networks”
Systems and Network Administrator, The Scientific and Technological Research Council of Turkiye
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Mirek Walukiewicz – “Virtual IP Load Balancer using P4”
Principal Engineer, Altera
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Phani Suresh Paladugu – “Enabling Programmable Performance: Memory and Interconnect Innovation for AI-Centric Data Planes”
Executive Director – Product Management, Synopsys
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Jitesh Sreedharan Nambiar – “AI‑Enabled BOM Lifecycle for P4‑Programmable Infrastructure Reliability”
BE Graduate, Mumbai University
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Mohammad Firas Sada – “Cross-Federated P4 Research Testbed for Wide-Area Programmable Networking Experiments”
Data Science Research Specialist, San Diego Supercomputer Center
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Shaan Nagy | Ali Kheradmand – “Automated Switch Validation with Path-Complete Testing at Scale”
PhD Student, UCSD | Senior Software Engineer, Google
View Video | View Slides
Amith Gspn – “Real-Time Encrypted Traffic Classification with P4 and DPDK”
Graduate Student Assistant and PhD Student, University of South Carolina
View Video | View Slides

P4 Demo
Advay Singh | Ali Imran | Muhammad Shahbaz – “Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern SmartNICs”
Research Assistant | Graduate Student Research Assistant | Assistant Professor EECS – Computer Science and Engineering, University of Michigan
View Demo
General Chair
Fernando Ramos, University of Lisbon
Program Committee
Amedeo Sapio, NVIDIA
Andy Fingerhut, Cisco
Ben Pfaff, Feldera
Chris Sommers, KeySight
Gianni Antichi, Politecnico di Milano & Queen Mary University of London
Jonathan DiLorenzo, Google
Mario Baldi, NVIDIA
Muhammad Shahbaz, University of Michigan
Vladimir Gurevich, P4ica
All attendees and participants are expected to behave in accordance with professional standards and the Linux Foundation Events Code of Conduct – for more information, see the full Code here.

P4 Developer Days - P4sim: Protocol-Independent Packet Processors in ns-3
2025-10-29 08:00
P4 Developer Days webinar, “P4sim: Protocol-Independent Packet Processors in ns-3”
Date: October 29, 2025
Time: 8:00am Pacific
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VIEW SLIDES
Abstract
Network simulation plays a crucial role in evaluating new architectures, protocols, and algorithms before deployment. While ns-3 is one of the most widely used discrete-event network simulators, it lacks native support for programmable data plane behaviors described in P4. P4sim addresses this gap by integrating P4’s protocol-independent, table-driven packet processing model into the ns-3 simulation framework. This talk introduces the architecture and capabilities of P4sim, demonstrates how developers can prototype and test P4 programs in simulation environments, and presents example use cases such as custom switching logic and in-band telemetry. Attendees will learn about the architecture and design of P4sim, which supports P4 architectures like V1Model, PSA, and PNA. The talk highlights its integration with ns-3 and showcases practical use cases. P4sim enables early development and testing of P4 programs without hardware, making it ideal for researchers and developers in programmable networking and simulation.
Speaker

Mingyu Ma is a Ph.D. researcher at Technische Universität Dresden, Germany, focusing on computer networks, programmable data planes, and simulation platforms. Mingyu has been actively involved in bridging the gap between research prototypes and real-world deployments, with hands-on experience in P4, ns-3 and traffic control. He regularly contributes to academic conferences and open-source communities related to network systems and simulation.

P4 Developer Days - AR/CG Network Traffic Classification in Programmable Dataplane
2025-11-12 08:00
P4 Developer Days webinar, “AR/CG Network Traffic Classification in Programmable Dataplane”
Date: November 12, 2025
Time: 8:00am Pacific
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Abstract
In this presentation, we explore the importance of classifying AR/CG traffic directly within the network device to enable low-latency, intelligent forwarding. We outline the end-to-end process of feature extraction and deployment within a programmable data plane, focusing on how key traffic features are computed and mirrored in P4-enabled switches. We also discuss the training of machine learning models tailored for the P4 data plane and their use in online pattern matching. Finally, we introduce our key contributions, including the extracted features, developed codebase, and publicly available repositories.
Speaker
Alireza Shirmarz received his B.Sc. in Computer Engineering from Shahed University in 2009 and his M.Sc. in Network Engineering from Amirkabir University of Technology (Tehran Polytechnic) in 2014. He earned his Ph.D. in Computer Engineering from IAU-Tehran North Branch in 2020. Since 2014, he has been actively teaching undergraduate courses in computer science and engineering and has been involved in graduate and Ph.D. supervision since 2020.
His research focuses on the intersection of networking and AI/ML, particularly in optimizing Quality of Experience (QoE) for real-time and interactive applications in future networks, including 6G. He specializes in intelligent data plane solutions, SDN architectures, and QoS/QoE management. Currently, he is a Postdoctoral Researcher at UFSCar, advancing AI/ML applications in networking.

P4 Developer Days - Implementation of Periodic Behavior with P4: Challenges and Solutions on Intel Tofino with Application in Time-Sensitive Networking (TSN)
2025-11-19 08:00
P4 Developer Days webinar, “Implementation of Periodic Behavior with P4: Challenges and Solutions on Intel Tofino with Application in Time-Sensitive Networking (TSN)”
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Abstract
Implementing periodic time behavior in hardware data planes is challenging due to limited arithmetic capabilities such as the lack of modulo operations, restricted timestamp precision, and resource constraints. This talk presents a general mechanism for implementing periodic time logic in P4, i.e., enabling data plane behavior that repeats in fixed time intervals, applicable to a broad range of time-aware applications. The mechanism enables periodic packet matching by mapping absolute timestamps to relative positions within a hyperperiod. To emulate hyperperiod boundaries, we leverage the switch’s internal packet generator to generate periodic trigger packets that act as time anchors for computing relative timestamps.

As a concrete use case, we apply this mechanism to implement Per-Stream Filtering and Policing (PSFP) as defined in IEEE 802.1Qci. Our implementation on Intel Tofino™ hardware demonstrates reliable time-based gating at line rate. Finally, we discuss how this periodicity mechanism can be extended to implement additional time-sensitive features such as the Time-Aware Shaper (TAS), offering a scalable foundation for deterministic network behavior in P4-based systems.

Speaker
Fabian Ihle received his bachelor’s (2021) and master’s degrees (2023) in computer science at the University of Tuebingen. Afterwards, he joined the communication networks research group of Prof. Dr. Habil Michael Menth as a Ph.D. student. His research interests include software-defined networking, P4-based data plane programming, resilience, and Time-Sensitive Networking (TSN).

P4 Developer Days - QuIP: A P4 Quantum Internet Protocol Prototyping Framework
2025-12-03 08:00
P4 Developer Days webinar, “QuIP: A P4 Quantum Internet Protocol Prototyping Framework”
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Abstract

Quantum entanglement is so fundamentally different from a network packet that several quantum network stacks have been proposed; one of which has even been experimentally demonstrated. Several simulators have also been developed to make up for limited hardware availability, and which facilitate the design and evaluation of quantum network protocols. However, the lack of shared tooling and community-agreed node architectures has resulted in protocol implementations that are tightly coupled to their simulators. Besides limiting their reusability between different simulators, it also makes building upon prior results and simulations difficult. To address this problem, we have developed QuIP: a P4-based Quantum Internet Protocol prototyping framework for quantum network protocol design. QuIP is a framework for designing and implementing quantum network protocols in a platform-agnostic fashion. It achieves this by providing the means to flexibly, but rigorously, define device architectures against which quantum network protocols can be implemented in the network programming language P416. QuIP also comes with the necessary tooling to enable their execution in existing quantum network simulators. We demonstrate its use by showcasing V1Quantum, a completely new device architecture, implementing a link- and network-layer protocol, and simulating it in the existing simulator NetSquid.
Speaker
Wojciech Kozlowski is the Quantum Communication Topic Lead at SURF. He completed his MSci in Theoretical Quantum Physics at the University of Cambridge and his PhD in Atomic and Laser Physics at the University of Oxford. Since then, Wojciech has been involved with networks, both classical and quantum. After his PhD he joined Metaswitch in London where he worked as a software engineer developing (classical) control planes. In 2019, Wojciech moved to the Netherlands where he worked as a postdoc and later quantum network engineer at the TU Delft before joining SURF in 2024.

P4 Developer Days - Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA based SmartNICs
2026-02-04 08:00 - 09:00
Register to attend this P4 Developer Days webinar, “Programmable Data Planes for the Cloud Era: Harnessing P4 on FPGA-based SmartNICs”

Date: February 4, 2026
Time: 8:00am Pacific
Abstract
The exponential growth of cloud-native services, 5G connectivity, and data-intensive applications is driving unprecedented demand for high-throughput and flexible packet processing. Traditional fixed-function ASIC solutions, while performant, lack the adaptability to address emerging tunnelling protocols, dynamic QoS enforcement, and evolving custom workloads. P4, an open and protocol-independent programming language for the data plane, directly addresses these limitations by enabling developers to rapidly define and deploy advanced packet pipelines without RTL complexity. By combining FPGA Vendors P4 Compilers like Altera’s P4 Suite with iW-Fibre SmartNICs, operators can synthesize programmable pipelines that sustain line-rate performance while remaining fully adaptable.
Demonstration of the use cases – including checksum verification, IP-in-IP tunnelling, VXLAN encapsulation/decapsulation, and standards-based QoS metering—illustrate how P4 empowers service providers and data centers to stay agile, scalable, and future-ready.
Speaker
Chethan T V is an Electronics an Communications Engineer possessing diverse experience in embedded industry as a digital design engineer with extensive expertise in FPGA design flow and SoC lifecycle. With strong project management skills, he has led various challenging projects from conceptualization stage to execution and delivered successful products in the field of defense, video, military & commercial sectors. He is an Associate Director, FPGA BU, iWave Global – leading the Smart-NIC division from the ground up, building a high-performing team, and driving strategic projects in next-generation networking.

P4 Developer Days - P4Muse (P4 Modularity and Unification for Seamless Extensibility)
2026-03-04 08:00 - 09:00
Register to attend this P4 Developer Days webinar, “P4Muse (P4 Modularity and Unification for Seamless Extensibility”
Date: March 4, 2026
Time: 8:00am Pacific
Abstract

Domain-specific programming languages such as P4 enable flexible and high-performance packet processing in programmable network data planes. However, most P4 programs remain monolithic, limiting the development of modular and reusable protocols and libraries. Introducing modularity to P4 has been challenging because existing approaches—such as trans-compilers and virtualization—operate outside the P4 language and compiler, reducing backward compatibility and extensibility. P4Muse (P4 Modularity and Unification for Seamless Extensibility) addresses this challenge by introducing a compiler-managed approach to modularity within the P4C compiler. Without requiring any new syntax or annotations, P4Muse introduces new compiler passes for automatic code merging, enabling modular design, reuse, and seamless integration of complex network functionalities. Our results show that P4Muse effectively supports modular P4 program development without altering existing P4 syntax, providing a robust solution that significantly improves code reusability, flexibility, and extensibility while maintaining backward compatibility.

Speakers
Mohsen Rahmati is a Ph.D. candidate in Computer Engineering at Polytechnique Montréal, supervised by Professors Yvon Savaria, François-Raymond Boyer, and Jean-Pierre David. His research focuses on compiler design for programmable networks, emphasizing modularity and reusability in the P4 language. He is the creator of P4Muse, a compiler-managed modularity framework (accepted in IEEE Access, 2025), and P4O2, an object-oriented-inspired modularity in P4 currently under review at IEEE Access.

François-Raymond Boyer received B.Sc. and Ph.D. degrees in computer science from Université de Montréal, Montreal, QC, Canada, in 1996 and 2001, respectively. Since 2001, he has been with Polytechnique Montréal, Montréal, where he is currently a Professor with the Department of Computer and Software Engineering. He has authored or co-authored more than 30 conference and journal papers. His current research interests include microelectronics, performance optimization, parallelizing compilers, digital audio, and body motion capture. He is a member of Regroupement Stratégique en Microélectronique du Québec, Groupe de Recherche en Microélectronique et Microsystèmes, and Observatoire Interdisciplinaire de Création et de Recherche en Musique.

P4 Developer Days - SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate
2026-03-19 08:00 - 09:00
Register to attend this P4 Developer Days webinar, “SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate”

Abstract
Machine learning is increasingly used in programmable data planes, such as switches and smartNICs, to enable real-time traffic analysis and security monitoring at line rate. Decision trees (DTs) are particularly well-suited for these tasks due to their interpretability and compatibility with the Reconfigurable Match-Action Table (RMT) architecture. However, current DT implementations require collecting all features upfront, which limits scalability and accuracy due to constrained data plane resources. This paper introduces SpliDT, a scalable framework that reimagines DT deployment as a partitioned inference problem over a sliding window of packets. By dividing inference into sequential subtrees—each using its own set of top-k features—SpliDT supports more stateful features without exceeding hardware limits. An in-band control channel manages transitions between subtrees and reuses match keys and registers across partitions, implemented using P4 for packet recirculation and control-plane coordination. This design allows physical resources to be shared efficiently while maintaining line-rate processing. To maximize accuracy and scalability, SpliDT employs a custom training and design-space-exploration (DSE) workflow that jointly optimizes feature allocation, tree depth, and partitioning. Evaluations show that SpliDT supports up to 5x more features, scales to millions of flows, and outperforms baselines, with low overhead and minimal time-to-detection (TTD).

Speaker
Murayyiam Parvez is a Ph.D. candidate in the Department of Computer Science at Purdue University, advised by Professor Muhammad Shahbaz and Professor Sonia Fahmy. Her research focuses on designing the next generation of hybrid software–hardware abstractions and architectures for emerging network security and machine learning applications, with an emphasis on leveraging programmable switches to enable high-performance, in-network intelligence.

Register to attend this webinar!
