ACM SIGCOMM 2019 Full-Day Tutorial on Programming the Network Data Plane
2019-08-23 08:30 - 17:00 UTC
Held at Shangri-La Hotel Beijing on Friday, August 23, 2019
Expectations
Attendees will be expected to have basic familiarity with the P4 lanaguage. Novice participants without any prior P4 experience are encouraged to refer to the Getting Started wiki page.
Attendees will also be expected to bring their own laptops. We will provide a VM image containing all the necessary packages and tools. The P4 specification is publicly available at the P4 website under an Apache license. Key development tools (front-end compiler and software switch capable of running P4 programs) are available as open-source tools (http://github.com/p4lang).
Instructions
In order to ensure that you arrive prepared for the tutorial we ask that you please follow the instructions listed on our GitHub repository.
If you attend and complete the P4 tutorial and you would like to receive a certificate of completion from P4.org, please send an email to sibanez@stanford.edu indicating your request.
Agenda

8:30am – 9:30am

P4 Language Overview

9:30am – 10:00am

Collaborative Lab Exercises – Part I

10:00am – 10:30am

Tea/Coffee Break

10:30 – 12:00pm

Collaborative Lab Exercises – Part II

12:00pm – 1:30pm

Lunch

1:30pm – 3:00pm

Mini Research Workshop – Part I

Leveraging P4 to Automatically Validate Networking Switches. Stefan Heule, Konstantin Weitz, Waqar Mohsin, Lorenzo Vicisano, Amin Vahdat (Google).
Mimic P4 Model. Le Tian (Information Engineering University), Pengshuai Cui (PLA Strategic Support Force Information Engineering University), Yuxiang Hu (PLA Strategic Support Force Information Engineering University)
Taurus: An Intelligent Data Plane. Tushar Swamy, Alexander Rucker, Muhammad Shahbaz, and Kunle Olukotun (Stanford University)
100Gbps P4-enabled Smart NIC: Architecture and Challenges on Datapath implementation in FPGA. Yan Yan (Raymax Technology)

3:00pm – 3:30pm

Break

3:30pm – 5:00pm

Mini Research Workshop – Part II

Non-invasive Campus Deployment of P4-based Network Measurement. Xiaoqi Chen (Princeton University)
Performant and Flexible DDoS Defense with Programmable Switches. Zaoxing Liu (Carnegie Mellon University), Georgios Nikolaidis (Barefoot Networks), Jeongkeun Lee (Barefoot Networks), Changhoon Kim (Barefoot Networks), Xin Jin (Johns Hopkins University), Minlan Yu (Harvard University), Vyas Sekar (Carnegie Mellon University)
Magellan: A Compiler and Runtime for High-Level Programming of Highly Programmable Network Data Planes. Y. Richard Yang (Yale University)
Redesigning Sketch Data Structures for Programmable Data Plane Devices. Vladimir Braverman (Johns Hopkins University)

Organizers

Stephen Ibanez (Stanford University)
Changhoon Kim (Barefoot Networks)

2nd P4 Workshop in Europe (EuroP4)
2019-09-23 08:30 - 18:00
A presentation by the P4 Language Consortium and ONF in conjunction with ANCS 2019
Held at Cambridge, UK on September 23, 2019
EuroP4 2019 is the second P4 Language Consortium event in Europe.
It aims to bring together P4 and P4->NetFPGA researchers from Europe and from around the world, and to foster the growth of the P4 Community.
Topics of an interest include, but are not limited to:

All aspects of P4-based network protocol research including design, specification, verification, implementation, measurement, testing, and analysis.
Contributions to network architecture using P4, e.g., specific algorithms and protocols for network virtualization or future Internet architectures.
New applications and in-network computing enabled by P4
P4-based and P4-NetFPGA based programmable data planes
End-host networking with P4
Tools and frameworks for development using P4
Performance analysis and measurement of P4-based designs and systems
Contributions to the evolution of the P4 language

Venue
University of Cambridge
Department of Computer Science and Technology
The Computer Laboratory
William Gates Building
15 JJ Thomson Avenue, Cambridge CB3 0FD
Agenda

8:30 – 9:15am

Registration and Breakfast

9:15 – 9:30

Welcome and Introductions

9:30 – 10:30

Keynote: Undefined behaviours in P4 progams: find them, fix them or exploit them. (Slides) Speaker: Professor Costin Raiciu (University Politehnica of Bucharest)

Abstract

Biography

10:30 – 11:00

Coffee break

11:00 – 12:15

Offloading data plane functions to the multi-tenant Cloud Infrastructure using P4. (Paper) (Slides)
Tomasz Osinski (Orange Labs & Warsaw University of Technology), Mateusz Kossakowski (Orange Labs & Warsaw University of Technology), Halina Tarasiuk (Warsaw University of Technology), Roland Picard (Orange Labs)
P4DNS: In-Network DNS. (Paper) (Slides)
Jackson Woodruff (University of Cambridge), Murali Ramanujam (University of Cambridge), Noa Zilberman (University of Cambridge)
Cryptographic Hashing in P4 Data Planes. (Paper) (Slides)
Dominik Scholz (Technical University of Munich), Andreas Oeldemann (Technical University of Munich), Fabien Geyer (Technical University of Munich), Sebastian Gallenmüller (Technical University of Munich), Henning Stubbe (Technical University of Munich), Thomas Wild (Technical University of Munich), Andreas Herkersdorf (Technical University of Munich), Georg Carle (Technical University of Munich)

12:15 – 13:45

Lunch break

13:45 – 15:00

daPIPE – A Data Plane Incremental Programming Environment. (Paper) (Slides)
Mario Baldi (Politecnico di Torino)
Random Linear Network Coding on Programmable Switches. (Paper) (Slides)
Diogo Gonçalves (University of Lisbon), Salvatore Signorello (University of Lisbon), Fernando M.V. Ramos (University of Lisbon), Muriel Medard (MIT)
Towards Understanding the Performance of P4 Programmable Hardware. (Paper) (Slides)
Hasanin Harkous (Technical University of Munich/ Nokia Bell Labs), Michael Jarschel (Nokia Bell Labs), Mu He (Technical University of Munich), Rastin Pries (Nokia Bell Labs), Wolfgang Kellerer (Technical University of Munich)

15:00 – 15:15

Posters and Demos introduction and pitch

15:15 – 16:15

Coffee break with Posters and Demos

16:15 – 17:15 (No Proceedings Track)

Towards Neural Network Inference on Programmable Switches. Jonatan Langlet (Karlstad University), Andreas Kassler (Karlstad University), Deval Bhamare (Karlstad University)
In-Network Traffic Redundancy Elimination over Programmable Data Plane. Hongrok Choi (Korea University), Seokwon Jang (Korea University), Sangheon Pack (Korea University)
Estimation of logarithmic and exponential functions entirely in P4-programmable data planes. Damu Ding (FBK CREATE-NET research center), Marco Savi (FBK CREATE-NET research center), Domenico Siracusa (FBK CREATE-NET research center)
Resource-Efficient Service Function Chaining in Programmable Data Plane. Hochan Lee (Korea University), Jaewook Lee (Korea University), Haneul Ko (Korea University), Sangheon Pack (Korea University)
How NRENs can benefit from P4. Mauro Campanella (GARR), Pavel Benacek (CESNET), Ivana Golub (PSNC), Xavier Jeannin (RENATER), Damian Parniewicz (PSNC), Marco Savi (FBK), Frederic Loui (RENATER)

17:15 – 17:30

Closing

18:00 onwards

Social Event This event will be held in conjuction with the IEEE ANCS reception.

Accepted Posters

P4MT: Multi-Tenant Support Prototype for International P4 Testbed. Jim Hao Chen (iCAIR/Northwestern University), Buck Chung (National Chiao Tung University), Chien-Chao Tseng (National Chiao Tung University), Joe Mambretti (iCAIR/Northwestern University)
Sketch-based Entropy Estimation for Network Traffic Analysis using Programmable Data Plane ASICs. Yu-Kuen Lai (Chung-Yuan Christian University), Ku-Yeh Shih (Chung-Yuan Christian University), Po-Yu Huang (Chung-Yuan Christian University), Ho-Ping Lee (Chung-Yuan Christian University), Yu-Jau Lin (Chung-Yuan Christian University), Te-Lung Liu (Narlabs), Jim Chen (Northwestern University)
Graph-to-P4: A P4 boilerplate code generator for parse graphs. Eder Ollora Zaballa (Technical University of Denmark), Zifan Zhou (Technical University of Denmark)
Asynchronous Extern Functions in Programmable Software Data Planes. Daniel Horpacsi (ELTE Eötvös Loránd University, Budapest, Hungary), Sandor Laki (ELTE Eötvös Loránd University, Budapest, Hungary), Peter Voros (ELTE Eötvös Loránd University, Budapest, Hungary), Mate Tejfel (ELTE Eötvös Loránd University, Budapest, Hungary), Gergely Pongracz (Ericsson Research), Laszlo Molnar (Ericsson Research)

Accepted Demos

P4-NetFPGA-based network slicing solution for 5G MEC architectures. Ruben Ricart-Sanchez (University of the West of Scotland), Pedro Malagon (Universidad Politecnica de Madrid), Jose M. Alcaraz-Calero (University of the West of Scotland), Qi Wang (University of the West of Scotland)
Using P4 on Fixed-Pipeline and Programmable Stratum Switches. Brian O’Connor (ONF), Yi Tseng (ONF), Maximilian Pudelko (ONF), Alireza Ghaffarkhah (Google), Devjit Gopalpur (Google)
How to measure the speed of light with programmable data plane hardware?. Ralf Kundel (TU Darmstadt), Fridolin Siegmund (TU Darmstadt), Boris Koldehofe (TU Darmstadt)

General Chairs

Noa Zilberman, University of Cambridge
Robert Soulé, Yale University

Program Chairs

Gianni Antichi, Queen Mary University of London
Fernando Ramos, University of Lisbon

Web Chair

Salvatore Signorello, University of Lisbon

Technical Program Committee

Gordon Brebner, Xilinx
Paolo Costa, Microsoft Research
Jon Crowcroft, University of Cambridge
Ben Pfaff, VMware
Georgios Nikolaidis, Barefoot Networks
Marco Chiesa, KTH
Gabor Retvari, University of Budapest
Roberto Bifulco, NEC
Ran Ben Basat, Harvard University
Andreas Kassler, Karlstads University
Mario Baldi, Politecnico di Torino
Christian Rothenberg, University of Campinas
Muhammad Shahbaz, Stanford University
Aurojit Panda, New York University
Marcin Wojicik, University of Cambridge

Special Thanks to our Sponsors:

P4 Hackathon in Amsterdam
2019-10-18 09:00 - 18:00
An event organized by the P4 Education Working Group
Held in Amsterdam, The Netherlands on October 18th, 2019
The P4 Hackathon aims to develop novel, proof-of-concept data plane applications, and to support the open-source community through the development of tools and infrastructure.
The hackathon is intended for P4 users of all levels – from beginners to experts. We are keen to meet new people, see new faces, and create new collaborations between (and within) academia and industry!
Venue
KPN Teleportboulevard 121 1043 EJ Amsterdam Netherlands
Agenda

9:00 – 9:15

Registration
Coffee & Light Snacks

9:15 – 9:30

Welcome and Introductions

9:30 – 13:00

P4 introductory course for beginners
Break into interest groups and hack!

13:00 – 14:00

Lunch!

14:00 – 14:15

Progress discussion & QA session

14:15 – 17:45

Further P4/P4Runtime tutorials
More hacking

17:55 – 18:00

Closing

Diversity and inclusivity
The P4 hackathon aims to increase the diversity and inclusivity of the P4 community. Everyone should feel welcome taking part in the event, and we will enforce a strict no-harrasement code of conduct.
Please contact aaron@aagico.berlin if you are unable to attend because of travel or accomodation costs
Organization

Aaron A. Glenn, AAGlenn Internetworking Company
Noa Zilberman (chair), University of Cambridge (P4 Education Working Group)
Robert Soulé (chair), Yale University (P4 Education Working Group)

Special Thanks to our Sponsors:

Thank you to KPN for providing the event location and sponsoring food & drink in full.

P4 Expert Roundtable Series
2020-04-28 08:00 - 2020-04-29 08:00
The P4 Expert Roundtable Series was a virtual event that included keynotes, plenary, and panel discussions relevant to the P4 community. The video recordings and slides are now available for on-demand access below, or view complete YouTube playlist.

Keynotes

P4 at the Edge
Nate Foster, Associate Professor, Computer Science, Cornell University
Slides

Using P4 & P4 Runtime for Optimal L3 Routing
Stefan Heule, Software Engineer, Google
Slides

Future of Programmable Packet Processing
Chang Kim, CTO Applications, Barefoot Division, Intel
Slides

P4 Evolution – From Packet Processing to Message Processing
Vipin Jain, Founder & CTO, Pensando
Slides

Plenary Sessions

Title
Slides
Video

How is P4 Evolving as a Language

Moderator: Andy Fingerhut, Cisco
Tomasz Osiński, Orange
Eric Campbell, Cornell University

Slides
Video

P4 Use Cases in Programmable Switching

Moderator: Prem Jonnalagadda, Intel
Guy Caspary, Cisco
Paola Grosso, University of Amsterdam
Arkadiy Shapiro, Intel

Slides
Video

P4 Use Cases in Operator Networks

Moderator: Brian O’Connor, ONF
Suresh Krishnan, Kaloom
Vijay Sivaraman, Canopus Networks

Slides
Video

P4 Use Cases in Programmable NICs

Moderator: Gordon Brebner, Xilinx
John Cruz, Pensando
Mario Baldi, Pensando

Slides
Video

Closing the Loop: Network Control in the Data Plane

Moderator: Jen Rexford, Princeton University
Daniel Alvarez, Intel

Slides
Video

Plenary Sessions

Title
Slides
Video

Programmable In-Network Security for Context-Aware BYOD Policies

Qiao Kang, Rice University
Srinivas Narayana Ganapathy, Rutgers University

Slides
Video

Efficient P4+FPGA-based Forwarding for SCION, a Path-Aware Internet Architecture

Kamila Součková, ETH Zurich
Steve Ibanez, Stanford University

Slides
Video

PBT-on-Demand on Mellanox P4-Capable Hybrid Switch

Itzik Ashkenazi, Technion – Israel Institute of Technology
Matty Kadosh, Mellanox Technologies
Muhammad Shahbaz, Stanford University

Slides
Video

Realizing Source Routed Multicast Using Mellanox’s Programmable Hardware Switches

Yonatan Piasetzky, Mellanox Technologies
Muhammad Shahbaz, Stanford University
Praveen Tammana, Princeton University

Slides
Video

NetWarden: Mitigating Network Covert Channels While Preserving Performance

Jiarong Xing, Rice University
Alan Liu, Carnegie Mellon & Boston University

Slides
Video

A Journey from OpenFlow to P4: Improved Performance and Reduced Development Time

Jeff Elpern, NoviFlow
Mihai Budiu, VMware Research

Slides
Video

FlowPulse: Traffic Classification Using P4 and ML

Himal Kumar, Canopus Networks
Vijay Sivaraman, Canopus Networks
Brian O’Connor, ONF
Prem Jonnalagadda, Intel

Slides
Video

Mathematical Operations in Programmable Switches Using TCAMs

Mojtaba Malekpourshahraki, University of Illinois at Chicago
Brent Stephens, University of Illinois at Chicago
Srinivas Narayana Ganapathy, Rutgers University

Slides
Video

Towards an Open P4 Programmable Hardware Platform

Gordon Brebner, Xilinx
Stephen Ibanez, Stanford University

Slides
Video

Programmable Data Plane Architecture for the Network Edge

Mario Baldi, Pensando Systems
Mina Tahmasbi Arashloo, Cornell University

Slides
Video

Building and Delivering a P4-based Network Tester

Ram Murthy, Keysight Technologies
Praveen Tammana, Princeton University

Slides
Video

Offloading Media Traffic to Programmable Data Plane Switches

Elie Kfoury, University of South Carolina
Mina Tahmasbi Arashloo, Cornell University

Slides
Video

Advanced Congestion Control with Programmable Switches

Jeongkeun “JK” Lee, Barefoot Division at Intel
Muhammad Shahbaz, Stanford University

Slides
Video

Sponsors

3rd P4 Workshop in Europe (EuroP4) 2020
2020-09-12 08:00 - 17:00
EuroP4 2020 is the third P4 Language Consortium event in Europe. It aims to bring together P4 and P4->NetFPGA researchers from Europe and from around the world, and to foster the growth of the P4 Community.

2021 P4 Workshop
2021-05-18 08:00
The 2021 P4 Workshop was an exciting and informative virtual event that incorporated insights and perspectives from P4 community members around the world, with focused segments on:

P4 language
P4 targets
P4 use cases
P4 demos
P4 target tutorials

It included live keynotes as well as on-demand tech talks, demos, and tutorials – all the content is now available on-demand below.

LIVE KEYNOTES

Title & Speaker
Video
Slides

FROM PROGRAMMABLE SWITCHES TO PROGRAMMABLE NETWORKS
Nate Foster, Associate Professor Computer Science, Cornell University

P4 AT INTEL
Guido Appenzeller, CTO, Data Platforms Group, Intel

THE VALUE OF P4 PROGRAMMABILITY AT THE NETWORK EDGE
Prem Jain, CEO & Co-Founder, Pensando

APPROXIMATION IN PROGRAMMABLE DATA PLANE
Minlan Yu, Associate Professor, Harvard University

PINS P4 INTEGRATED NETWORK STACK
Mythil Raman, Director Switch Infrastructure, Google
Konstantin Weitz, Software Engineer, Google

SD-FABRIC PROGRAMMABLE FABRIC FOR DATACENTERS
Timon Sloane, VP Marketing & Ecosystem, ONF
Charles Chan, MTS, ONF

PROGRAMMABLE NETWORKING – OUR JOURNEY
Yiqun Cai, VP, Alibaba

PROGRAMMABILITY AND NETWORKING: WHY DO WE BOTHER?
Pere Monclus, VP & CTO Network and Security, VMware

HIGHER-ORDER TELEMETRY IN THE DATA PLANE
Jennifer Rexford, Gordon U.S. Wu Professor of Engineering, Department Chair, Princeton University

P4: TWO SIDES OF THE SAME COIN
Anja Feldmann, Director, Max-Planck

DEEPLY PROGRAMMABLE 5G EDGE CLOUD FABRIC WITH P4
Oğuz Sunay, VP R&D, Mobility, ONF
Carmelo Cascone, MTS, ONF

INVITED TALKS

Title & Speaker
Video
Slides

P4 PRACTICE AT BAIDU
Gang Cheng, Distinguished Engineer, Baidu

PROGRAMMABLE DATA PLANES FOR CONVERGED ACCESS INFRASTRUCTURE
Murali Venkat, Principal Engineer, Cisco

PROGRAMMABILITY IN NICS FOR CONGESTION CONTROL AND TRANSPORT
Nandita Dukkipati, Principal Engineer, Google
Konstantin Weitz, Software Engineer, Google

NDP WITH SONIC-PINS: A LOW LATENCY AND HIGH PERFORMANCE DATACENTER TRANSPORT INTEGRATED INTO SONIC
Rong Pan, Fellow, Data Platform Group, Intel
Reshma Sudarshan, Director Applications Engineering, Intel

TECHNICAL TALKS

Title & Speaker
Video
Slides

THE FOUR-DIMENSIONAL P4 SWITCHES – BASIC INTRODUCTION
Paul Chang, CTO, Asterfusion

EXTENDING P4 TO REALIZE A SCALABLE FLOW CACHING MECHANISM
Angelo Tulumello, Network Software Engineer, Axbryd / University of Rome Tor Vergata

MEASURING BROADBAND EXPERIENCE USING P4-PUSH TELEMETRY
Himal Kumar, CTO, Canopus Networks

P4-PROGRAMMABLE SMARTNIC CONTROLLED BY ONOS
Artur Jaworski, Software Developer, CodiLime
Pawel Parol, Senior Network Engineer, CodiLime

REVITALIZING INDUSTRIAL NETWORKING WITH PROGRAMMABLE DATA PLANES
Sándor Laki, Assistant Professor, ELTE Eötvös Loránd University

P4PI: P4 ON RASPBERRY PI FOR NETWORKING EDUCATION
Sándor Laki, Assistant Professor, ELTE Eötvös Loránd University

WHAT’S NEXT FOR P4? A JOURNEY AROUND MISSING FEATURES
Gergely Pongracz, Expert of Programmable Networks, Ericsson Research

ROUTER FOR ACADEMIA RESEARCH AND EDUCATION
Frédéric Loui, Technical Leader, GÉANT

CAN P4 RUN ON “SWITCHY” CPUS?
Cristian Dumitrescu, Software Architect, Intel
Han Wang, Software Architect, Intel

PORTABLE NIC ARCHITECTURE UPDATE
Andy Fingerhut, Principal Engineer, Intel

REALIZING ONE BIG SWITCH AS PERFORMANCE ABSTRACTION USING P4
Jeongkeun “JK” Lee, Principal Engineer, Intel
Petr Lapukhov, Network Engineer, Facebook

PACKET DEDUPLICATION IN P4
Stefan Johansson, FPGA Architect, Keysight Technologies

COMMON INTERMEDIATE REPRESENTATION (COMMON IR)
Venkat Pullela, Co-Founder, OpenNets

FLEXIBLE AND EFFICIENT MEMORY SYSTEM FOR A HIGH PERFORMANCE PROCESSING PIPELINE
Mario Baldi, Distinguished Technologist, Pensando

QUADCOPTER IMPLEMENTATION OF AN IN-NETWORK CENTRALIZED COLLISION AVOIDANCE ALGORITHM IN PROGRAMMABLE DATA PLANES
Fabricio Rodriguez, PhD Student, UNICAMP

PL2: TOWARDS PREDICTABLE LOW LATENCY IN RACK-SCALE NETWORKS
Yanfang Le, PhD Student, Intel & University of Wisconsin-Madison

DEMONSTRATIONS

Title & Speaker
Video
Slides

WHEN SRV6 MEETS 5G CORE: IMPLEMENTATION & DEPLOYMENT OF A NETWORK SERVICE CHAINING FUNCTION IN SMARTNICS
Guilherme Matos, Masters Student, Federal University of São Carlos

GOODBYE SCAPY, HELLO SNAPPI – DATAPLANE TESTING FROM DC TO DAYLIGHT USING OPEN TRAFFIC GENERATOR API
Chris Sommers, Software Architect, Keysight Technologies
Ankur Sheth, Director Engineering, Keysight Technologies

TUTORIALS

Title & Speaker
Video
Slides

P416 PROGRAMMING FOR INTEL TOFINO USING INTEL P4 STUDIO
Vladimir Gurevich, Principal Engineer, Barefoot, Intel
Andy Fingerhut, Principal Engineer, Intel

P4-OVS TUTORIAL
Dan Daly, Intel
Brian O’Connor, MTS, ONF
Tomasz Osinski, MTS, ONF
Kossakowski Mateusz, Orange
Nupur Jain, Intel
Gerald Rogers, Intel
Namrata Limaye, Software Engineer, Intel

NOVISPEAKER: COMMERCIALLY SUPPORTED P4 DEVELOPMENT & DEPLOYMENT TOOLSET FOR THE BAREFOOT/INTEL TOFINO
Arun Paneri, Director Engineering, NoviFlow
Jeff Elpern, Director Product Management, NoviFlow

SPONSORS

More About Our Sponsors

APS Networks® is about more than just network disaggregation within switches or software-defined networking (SDN). We are using a blend of development skills in hardware, firmware/embedded, OS, and application software, to help open the world of closed networking. We are taking the pieces and putting them back together more securely, efficiently, and most importantly, as part of an open, collaborative community with our customers and partners.
Our vision includes hardware, open source, and programmability, all tailored to our customers’ business-specific requirements, to provide a stable and supported platform for open networking innovation. Our dedicated hardware solutions are built around enabling the latest open technologies to serve vertical industry needs.

APS Networks ® BF2556X-1T
Advanced Programmable
Switch

APS Networks ® BF6064X-T
Advanced Programmable
Switch

NoviFlow believes programmable pipeline processing will fundamentally change the way networking is done. This has led to the development of our NoviWare SDN NOS, CyberMapper controller family, and cybersecurity network solutions deployed around the world.
We also believe that healthy solution ecosystems are built using great development tools that flatten the learning curve, reduce development effort and time, and deliver a reliable deployment.
NoviFlow’s NoviSpeaker P4 Runtime Speaker provides the P4 community with a commercially supported development and deployment toolset covering the complete development cycle and making full use of advanced P4 and Tofino capabilities on commercially available white-box hardware.

Vector Data builds Carrier-Grade NFV hardware infrastructure. Vector Data’s leading server, network, and storage solutions are deployed in SDN and Edge environments worldwide. All products are offered individually or as part of a complete OpenPod solution and are available with AC or -48V DC power as well as NEBS, ETSI, VCCI, KC, and other telecom compliance certifications.
Some products, such as Vault Edge servers, are offered with additional options such as outdoor, pole mount, fully rugged, HVDC, and wide temperature. Vector Data is a new ONF member and looks forward to joining the community.

ACM SIGCOMM 2021
2021-08-23 10:00 - 2021-08-27 17:00
ONF projects are being highlighted in several of the ACM SIGCOMM 2021 sessions:
August 23, 2021 | 10:00am – 5:00pm EDT
Hackathon: P4 on Raspberry PI (P4Pi)
P4PI enables designing and deploying P4-based network devices using the Raspberry Pi platform and is based on the T4P4S compiler. P4PI is developed as part of the P4 Education Workgroup activities. The team aims to provide both educators and practitioners the knowledge and tools required to use P4PI in class and at home, including tutorials, sample code, tools and community support.
Check out the web page to learn more. Introductory videos can be accessed in a YouTube playlist.
August 23, 2021 | 1:40pm – 5:00pm EDT
Tutorial, “5G Connected Edge Cloud”

Describe 5G, breaking it down into components familiar to the SIGCOMM community.
Introduce the available open source software that implements these components.
Show how these building blocks can be assembled into a Kubernetes-based edge cloud.
Identify and discuss the systems research opportunities such a platform enables.

Check out the web page to learn more.
August 27, 2021 | 1:00pm – 5:00pm EDT
Tutorial: Network-Accelerated Distributed Deep Learning

An introduction on scaling distributed machine learning from a networking-centric perspective. Includes a walk through of through of different solutions for accelerating network communication beginning with in-network aggregation, describing SwitchML (a system for distributed machine learning that accelerates data-parallel training using P4 switches) as an example of co-design of programmable switch-based processing and end-host protocols.
Examination of into properties of the traffic and exploit the sparsity of gradient values. A description of OmniReduce, which evolves the concept of in-network aggregation and focuses on efficient collective operations for sparse data. We will close with lossy gradient compression techniques and the GRACE framework for implementing them.

Check out the web page to learn more.

Japan P4 User Group 2021
2021-10-21 08:00
The Japan P4 Users Association is hosting this virtual event annual event in Japan. Japanese integrators, carriers, service providers, researchers, and individuals will join the event to exchange information. The language for this event is Japanese.
Check out the event web page to view videos and slides from this event.

Sponsors
APRESIA Systems
Intel K.K.
Macnica, Inc. Altima Company
Net One Systems Co., Ltd.
Toyota Motor Corporation

OCP Global Summit 2021
2021-11-09 08:00 - 2021-11-10 08:00
ONF hosted a pavilion at the event featuring demos of several of our open source projects.

Aether: Software-Defined Private 5G
SD-Fabric: Full Stack P4 Programmable Network Fabric
SD-RAN: O-RAN Compliant nRT-RIC and xApps
PINS: Bringing P4 and SDN to SONiC
VOLTHA: Virtual OLT Hardware Abstraction for PON

Presentation: “P4 Integrated Network Stack (PINS)”
View Recording
Speakers:
Bhagat Janarthanan, Google
Reshma Sudarshan, Intel
Brian O’Connor, ONF
PINS is a P4Runtime based network switch stack built on top of the SONiC framework. The PINS stack combines the benefits of the SDN controller with SONiC and brings optionality to SDN networking. This presentation will cover the architecture, the high-level design, and the various supplementary features the team has implemented as part of the stack. We will also discuss in detail some of the use cases that are enabled by the PINS stack.
Demonstration by ONF
View Slides
Brian O’Conner, Daniele Moro, Don Newton, Niloofar Toorchi
The demonstration featured Weighted Cost MultiPath (WCMP) routing as a use case for PINS.

4th P4 Workshop in Europe (EuroP4) 2021
2021-12-13 10:15 - 17:45
DECEMBER 13, 2021 | VIRTUAL
The 4th European P4 Workshop (EuroP4) brought together networking researchers to discuss cutting-edge, P4-based, research. The workshop provided a venue for P4-based research and projects, a place to discuss P4-based tools, and the research community needs. The workshop aims to forge connections between researchers, introduce more networking researchers to the P4 community, and seed future top-tier publications and innovation.
EuroP4 was held in conjunction with ACM/IEEE ANCS’21.
General Chair
Fernando Ramos, University of Lisbon
Program Chairs
Mario Baldi, Pensando Systems
Ben Pfaff, VMware
Steering Committee
Robert Soulé, Yale University
Noa Zilberman, University of Oxford
Organizing Committee
Publicity Chair: Damu Ding, University of Oxford
Hotcrp Chair: Francisco Pereira, University of Lisbon
Technical Program Committee
Gianni Antichi, Queen Mary University of London
Mina Tahmasbi Arashloo, Cornell University
Giuseppe Bianchi, University of Rome Tor Vergata
Roberto Bifulco, NEC Laboratories Europe
Gordon Brebner, Xilinx
Mihai Budiu, VMware Research
Andrea Campanella, Open Networking Foundation
Mauro Campanella, GARR
Marco Chiesa, KTN Royal Institute of Technology
Nate Foster, Cornell University
Theo Jepsen, Stanford University
Sándor Laki, Eötvös Loránd University
Shir Landau-Feibish, Princeton University
Sebastiano Miano, Queen May University of London
Brian O’Connor, Open Networking Foundation
Gergely Pongrácz, Ericsson Research
Salvatore Pontarelli, Sapienza University
Gábor Rétvári, Budapest University of Technology and Economics
Christian Esteve Rothenberg, University of Campinas
Stefan Schmid, University of Vienna & TU Berlin
Agenda
10:15 – 10:30
Welcome and Introductions
Mario Baldi and Ben Pfaff
10:30 – 11:30
Keynote talk by Bruce Davie
Session Chair: Ben Pfaff
Title: Always in the Kitchen at Parties: Separating Guests from Infrastructure
Abstract: There is an emerging consensus that the services necessary to operate a cloud, including network virtualization, isolation of tenants, storage services, etc., are good candidates for offloading from the general-purpose servers that host guest workloads. These infrastructure (or “overhead”) services have historically run in the same servers that host guest workloads, but now the point of control is moving to IPUs (infrastructure processing units), DPUs (data processing units), and SmartNICs. The challenge is in developing offload processors that are both efficient for the required tasks and sufficiently flexible to allow continued innovation. This talk traces the long history of offloading services from the CPU to more specialised offload engines, and speculates on how this offloading trend will impact the architecture of future cloud data centres.
Bio: Bruce Davie is a computer scientist noted for his contributions to the field of networking. He recently co-founded (with Larry Peterson) Systems Approach, LLC, to produce open source books and educational materials. He is a former VP and CTO for the Asia Pacific region at VMware. He joined VMware during the acquisition of Software Defined Networking (SDN) startup Nicira. Prior to that, he was a Fellow at Cisco Systems, leading a team of architects responsible for Multiprotocol Label Switching (MPLS). Davie has over 30 years of networking industry experience and has co-authored 17 RFCs. He was recognized as an ACM Fellow in 2009 and chaired ACM SIGCOMM from 2009 to 2013. He was also a visiting lecturer at the Massachusetts Institute of Technology for five years. Davie is the author of multiple books and the holder of more than 40 U.S. Patents.
11:30 – 12:00
Virtual coffee break
12:00 – 13:30
Session 1: P4 Technology
Session Chair: Gianni Antichi
High-Performance Match-Action Table Updates from within Programmable Software Data
Planes
Balachandher Sambasivam, Maheswari Subramanian, Deb Chatterjee, Mallikarjuna Gouda,
Sosutha Sethuramapandian, Yogender Singh Saroha (Intel Corporation)
Writing P4 Compiler Backend for ASIC IPU
Balachandher Sambasivam, Maheswari Subramanian, Deb Chatterjee, Mallikarjuna Gouda,
Sosutha Sethuramapandian, Yogender Singh Saroha (Intel Corporation)
Generic change detection (almost entirely) in the dataplane
Gonçalo Matos (INESC-ID, Instituto Superior Técnico, Universidade de Lisboa); Salvatore Signorello
(LASIGE, Faculdade de Ciências, Universidade de Lisboa); Fernando M. V. Ramos (INESC-ID, Instituto
Superior Técnico, Universidade de Lisboa)
13:30 – 14:30
Lunch break
14:30 – 15:30
Session 2: Posters and Demos
Session Chair: Sebastiano Miano
Heavy Hitter Detection on Multi-Pipeline Switches
Fábio Luciano Verdi (UFSCar/KTH Royal Institute of Technology); Marco Chiesa (KTH Royal Institute of
Technology)
Realizing Zenoh with programmable dataplanes
Alexandre Santos, Jose Quevedo, Daniel Corujo (Universidade de Aveiro and Instituto de
Telecomunicações)
Towards a Framework for One-sided RDMA Multicast
Xin Zhe Khooi, Cha Hwan Song, Mun Choon Chan (National University of Singapore)
Kubernetes Load-Balancing and Policy Using P4
Nupur Jain, Anjali Singhai, Vinoth Kumar Chandra Mohan, Debashis Chatterjee, Dan Daly (Intel)
Towards a more programmable and performance-optimized Virtual Switch
Namrata Limaye (Cloud Software Architect, Intel); Debashis Chatterjee (Senior Director, Intel)
Achieving End-to-End Network Visibility with Host-INT
Tomasz Osiński (Open Networking Foundation & Warsaw University of Technology); Carmelo Cascone
(Open Networking Foundation)
15:30 – 16:00
Coffee break
16:00 – 17:30
Session 3: P4 Applications
Session Chair: Theo Jepsen
Mitigation of IPv6 Router Spoofing Attacks with P4
Moritz Mönnich, Nurefşan Sertbaş Bülbül, Doğanalp Ergenç, Mathias Fischer (Universität Hamburg)
Building an Internet Router with P4Pi
Radostin Stoyanov (University of Oxford); Adam Wolnikowski (Humatics); Robert Soulé (Yale
University); Sándor Laki (Eötvös Loránd University); Noa Zilberman (University of Oxford)
Networked Answer to “Life, The Universe, and Everything”
Giles Babich, Keith Bengston, Andrew Bolin, John Bunton, Yuqing Chen, Grant Hampson,
David Humphrey, Guillaume Jourjon (CSIRO)
17:30 – 17:45
Closing words

2021 P4 Workshop Taiwan
2021-12-21 08:00
The P4 community which includes both industry and academia, came together to share research and practical experience related to P4 technology and use cases. Check the agenda and presentations included as part of this forum which was held at National Yang Ming Chiao Tung University.

Presentations

Title
Video
Slides

Opening Ceremony
Jason Yi-Bing Lin, Lifetime Chair Professor, NYCU, Taiwan

Intel® Intelligent Fabric Vision and P4 Technology
Todd Koelling, Director of Marketing and Technology Planning, Intel

Remote Priority Flow Control towards Source Flow Control (SFC)
Jeremias Blendin, Staff Engineer, Intel

P4 Users Community Update, Japan
Kentaro Ebisawa, Principal Researcher, Toyota Motor Corporation

Next Generation P4 Equipment
Jian-Hao Chen, Sr. Engineer, Accton Technology Corporation

Net-Gen Cloud-FMC Far Edge Architecture
James Yeh, Kaloom

P4 SONiC
Jimmy Ou, Senior Engineer, Accton Technology Corporation

Botnet Traffic Detection
Meng-Hsun Tsai, Associate Professor, NCKU, Taiwan

Design and Implementation of P4 Virtual Networks
Bonnie Chen, ITRI, Taiwan

P4-IPS: Deploying Intrusion Prevention System with Machine Learning on P4 Switch
Charles Hung-Pin Wen, Distinguished Professor, NYCU, Taiwan

Longer Stay Less Priority: Flow length approximation used in traffic scheduling in Data Centers
Chien Chen, Jointly Appointed Professor, NYCU, Taiwan

P4-Enabled network Slicing and 5G User Plane Function
Chien-Chao Tseng, Professor, NYCU, Taiwan

Server Load Balancer Accelerator (SLBA) P4-based Solution
Petr Kastovsky, Software Product Manager, Intel

A Flow Control Scheme based on Per Hop and Per Flow in Commodity Switches for Lossless Networks
Shie-Yuan Wang, Professor, NYCU, Taiwan

SmartNICs Summit
2022-04-26 08:00
Don’t miss the P4 Workshop taking place at the SmartNICs Summit on Tuesday, April 26th, 1-pm.
Mario Baldi, Pensando (Moderator)
Gordon Brebner, AMD
Carmelo Cascone, Intel

Session Description:

P4 is a programming language for specifying how network devices such as switches, routers, and NICs process packets. Vendors have used it as the programming language of choice for many products, such as the Cisco Silicon One chipsets, the Barefoot Tofino switches, the Pensando Distributed Services Cards, the AMD SN1000 SmartNIC, and the Aruba CX 10000 smart switch. It is particularly useful for today’s applications that employ software-defined networking (SDN). Using P4 makes network devices easier to program, debug, document, maintain, and update. The main ideas behind P4 are:
– Close relationship with typical packet processing tasks. P4 programs specify how packet headers are parsed and what actions are taken based on field values.
– Protocol independence: Network devices are not tied to specific protocols.
-Target independence: Programmers can describe packet processing for any underlying hardware.
– Reconfigurability in the field: Programmers can change the way switches process packets after deployment.
The P4 ecosystem includes an extensive range of products, projects, and services. The P4 website (p4.org) is a great source to learn about P4 and join the community. P4’s current tasks include the definition of a Portable NIC Architecture (PNA). Special Feature: Attendees will have opportunities to write P4 code and corresponding control plane functions.

P4 2022 Workshop
2022-05-24 08:00 - 2022-05-26 08:00
The P4 2022 Workshop incorporates insights and perspectives from P4 community members around the world and encompass topics related to:

P4 language
P4 compile targets
P4 tool chain
P4 use cases & apps
Control plane or network OS for P4 targets

Check out all the talks from this exciting and informative event on-demand below! Or, view full YouTube playlist.

Keynotes

TITLE
VIDEO
SLIDES

Welcome to P4 Workshop 2022!
JK Lee, Program Chair, member of P4 TST, Senior Principal Engineering, Intel

P4 on the Move!
Andy Fingerhut, Principal Engineer, Intel

Programmable Network Devices: One Vendor’s Perspective
Kenneth Duda, Founder, CTO & SVP Software Engineering, Arista Networks

Panel – IPU/DPU
Brad Burres, Fellow, Intel
Matty Kadosh, Principle Architect, Nvidia
Krishna Doddapaneni, Co-founder, VP Software Engineering, Pensando
Gordon Brebner, Senior Fellow, AMD

Scaling SDN Policy Distribution
Ben Pfaff, Principal Researcher, VMware

Expanding the P4 Universe
Gordon Brebner, Senior Fellow, AMD

Programmable Networking for a Distributed Edge
Nick McKeown, SVP & GM and Senior Fellow, Network & Edge Group, Intel
Sachin Katti, CTO, Network & Edge Group, Intel

The Journey Towards Predictable Network in Alibaba Cloud
Dennis Cai, Head of Network Infrastructure, Alibaba

SONiC, Programmability & Acceleration
Xin Liu, Principal Product Manager, Microsoft

Language

TITLE
VIDEO
SLIDES

Extend P4 to Support Runtime Programmability – In Depth Talk
Yong Feng, Ph.D Student, Tsinghua University
Dr. Haoyu Song, Researcher, Futurwei Technologies

Applets, a Portability and Composability Solution for P4 – In Depth Talk
Venkat Pullela, Chief of Technology, Networking, Keysight
Surendra Anubolu, Distinguished Engineer, Broadcom

Primitives for Finite Field Arithmetic in Network Switches – In Depth Talk
Daniel Seara, MSc Student, IST, Universit of Lisbon
Bernardo Conde, Master Student, IST, Universit of Lisbon

NERPA: Network Programming with Relational and Procedural Abstractions – In Depth Talk
Debnil Sur, Senior Software Engineer, VMware

SuperP4: Preprocessor-Aware Syntax and Semantic Analysis for P4 Programs – Tech Brief
Kaarthik Alagappan, Graduate Research Assistant, University of Central Florida

P4RROT: Generating P4 Code for the Application Layer – Tech Brief
Csaba Györgyi, PhD Student, ELTE Eötvös Loránd University
Sandor Laki, Assitant Professor, ELTE Eötvös Loránd University

Target

TITLE
VIDEO
SLIDES

Connection Tracking Using P4 – In Depth Talk
Anjali Singhai Jain, Principle Engineer, Intel
Nishanth Bhat, Intel
Namrata Limaye, Intel

Speeding Up Network FPGA Design Using P4 – In Depth Talk
Bert Klaps, Senior Systems Engineer, Intel
Miroslaw Walukiewicz, Intel

Line Rate IPsec on a PNA-Compliant Packet Processing Pipeline – In Depth Talk
Sameer Kittur, Distinguished Engineer, Pensando Systems

P4 Over Linux TC – In Depth Tal
Jamal Hadi Salim, CEO, Mojatatu Networks

Develop Your CPU Network Stack in P4 – In Depth Talk
Cristian Dumitrescu, Software Architect for Packet Processing, Intel

P4 at the Interface Between NIC and Host – In Depth Talk
Raghava Sivaramu, Fellow, Pensando Systems

P4 in Open vSwitch with OfP4 – Tech Brief
Ben Pfaff, Researcher, VMware

Deep Dive & Getting Started with PSA Implementation for eBPF – Tutorial
Tomasz Osiński, Cloud Software Development Engineer, Intel
Mateusz Kossakowski, R&D Expert, Orange Labs Poland
Jan Palimaka, Chief R&D Specialist, Orange Labs Poland

PSA-eBPF: Portable Switch Architecture for eBPF – Tech Brief
Tomasz Osiński, Cloud Software Development Engineer, Intel
Mateusz Kossakowski, R&D Expert, Orange Labs Poland
Jan Palimaka, Chief R&D Specialist, Orange Labs Poland

Tool Chain

TITLE
VIDEO
SLIDES

p4testgen: Automated Test Generation for Real-World P4 Data Planes – In Depth Talk
Fabian Ruffy, Intern, Intel and PhD Student, NYU

Dynamic P4 Pipeline Configuration – In Depth Talk
Anjali Singhai Jain, Principle Engineer, Intel
Hari Thantry, Cloud Architect, Google

Differential Testing of P4 Implementations Using CI/CD – Tech Brief
Parisa Ataei, Postdoc Scholar, Cornell University

P4 Designer – Demo
Pratap Pellakuru, Development Tools Software Architect, Intel
Sharmila S., Cloud Software Development Engineer, Intel

Introducing IPDK – Tutorial
Deb Chatterjee, Senior Director of Engineering, Intel

Control Plane and NOS

TITLE
VIDEO
SLIDES

Evolving P4 Runtime From Switch to DPU – In Depth Talk
Milind Chabbi, Nvidia
Alan Lo, Compiler/Cloud Architect, Nvidia

Accelerating 5G (Mobile Core) Control Plane Using P4 – In Depth Talk
Jingqi Huang, Ph.D Student, Purdue University
Jiayi Meng, PhD Candidate, Purdue University

Table Driven Interface (TDI): Usages and Advantages – In Depth Talk
Sayan Bandyopadhyay, Cloud Software Developer, Intel
James Choi, Cloud Software Architect, Intel

PINS Update and Roadmap – In Depth Talk
Bhagat Janarthanan, Software Engineering Lead, Google
Brian O’Connor, Intel
Vamsi Punati, Google
Reshma Sudarshan, Director of Applications Engineering, Intel

PINS Packet I/O – In Depth Talk
Srikishen Pondicherry, Software Engineer, Google
Brian O’Connor, Intel
Don Newton, Intel

P4-OVS Split Architecture – In Depth Talk
Namrata Limaye, Engineering Manager/Tech Lead, Intel
Brian O’Connor, Intel
Ajay Kumar Dubey, Intel

P4 as a Single Source of Truth for SONiC DASH Use Cases on Both Softswitch and Hardware – In Depth Talk
Reshma Sudarshan, Director of Applications Engineering, Intel
Chris Sommers, Sr. Software Architect, Keysight

PINS Getting Started – Tutorial
Judy Snow, ONF
Brian O’Connor, Intel

Application

TITLE
VIDEO
SLIDES

P4 FOR NIC – A CLOUD PROVIDER PERSPECTIVE – In Depth Talk
Hari Thantry, Cloud Architect, Google

Inband Network Telemetry (INT): History, Impact and Future Directions – In Depth Talk
JK Lee, Sr. Principal Engineer, Intel
Mukesh Hira, Principal Engineer, Networking and Security, VMware

Network Programmability “Squared” – In Depth Talk
Satoru Matsushima, Technical Meister, Softbank

Architecture for Multi-Terabit Programmable Networking Functions – In Depth Talk
Petr Kastovsky, Product Marketing, Intel
Georgios Nikolaidis, Software Architect, Intel

A Change Detection Primitive for the Network Data Plane – In Depth Talk
Gonçalo Matos, Researcher, INESC-ID

M-PolKA: Enabling and Exploiting Multipath Stateless Source Routing for Programmable Data Planes – In Depth Talk
Rafael S. Guimaraes, Associate Professor, Instituto do Espirito Santo

PMNet: In-Network Data Persistence – In Depth Talk
Korakit Seemakhupt, Graduate Student, University of Virginia

Service Mesh P4 Data Plane – In Depth Talk
Anjali Singhai Jain, Principle Engineer, Intel
Mrittika Ganguli, Intel
Valas Valancius, Google
Nupur Jain, Intel

Towards In-Network Anomaly Detection – In Depth Talk
João Romeiras Amado, PhD Student, INESC-ID, University of Lisbon

Demo of L2 Forwarding + Vxlan with Control Packet Flow Using P4-OVS – Demo
Nupur Uttarwar, Cloud Software Engineer, Intel
Sandeep Nagapattinam, Cloud Software Engineer, Intel

P7 (P4 Programmable Patch Panel): An Instant 100G Emulated Network Testbed in a Pizza Box – Demo
Fabricio Rodriguez, PhD Student, UNICAMP

Enabling WCMP in SONiC Using PINS and ONOS – Demo
Nillofar Toorchi, MTS, ONF
Daniele Moro, Cloud Software Development Engineer, Intel

TCP-INT: Lightweight INT in TCP Transport – Demo
Simon Wass, Cloud Software Engineer, Intel
Miao Mao, Staff Software Engineer, Baidu

Open SRv6 Project: Open Source for P4-based Edge Router – Demo
Weiqiang Cheng, Principle Architect of IP Network, China Mobile
Jiang Liu, Professor, Beijing University of Posts and Telecommunications

Path Tracing: Revealing the Unknowns about ECMP – Demo
Ahmed Abdelsalam, Software Engineer, Cisco Systems

SD-Fabric (Part 1) – Tutorial
Carmelo Cascone, Cloud Software Development Engineer, Intel
Charles Chan, Cloud Software Development Engineer, Intel

SD-Fabric (Part 2) – Tutorial
Carmelo Cascone, Cloud Software Development Engineer, Intel
Charles Chan, Cloud Software Development Engineer, Intel

SD-Fabric (Part 3) – Tutorial
Carmelo Cascone, Cloud Software Development Engineer, Intel
Charles Chan, Cloud Software Development Engineer, Intel

ACM SIGCOMM 2022
2022-08-26 08:00
Hackathon: P4 on Raspberry PI for Networking Education
August 26th | 1:30pm – 6:00pm

P4Pi is a low cost, open source hardware platform intended for teaching and research purposes. P4Pi enables designing and deploying P4-based network devices using the Raspberry Pi board. By setting a target price tag of less than an academic book (under $100), P4Pi aims to enable a large number of academic institutes to provide hands-on experience in networking education. Furthermore, as P4Pi is based on the popular Raspberry PI platform, it appeals to other communities such as hobbyists and does not depend on a single-source provider.
P4Pi is developed as part of the P4 Education Workgroup activities. The team aims to provide both educators and practitioners the knowledge and tools required to use P4Pi in class and at home, including tutorials, sample code, tools and community support.
This hackathon aims to bring together members of the networking community for the following goals: (i) introduce P4Pi to networking researchers and educators, enable them to get started with the platform and practice its use in lab-like environment. (ii) develop more teaching and supporting materials for the P4Pi ecosystem. (iii) enable researchers from all levels of expertise to develop P4Pi-based concepts and early-stage projects, and to stimulate collaborations between new users.
Check out all the details here!

P4 Users Japan 2022
2022-10-20 08:00
The Japan P4 Users Group will be held as a hybrid event with both in-person and online access. This in-person event includes both presentations by industry and academic members of the P4 community who will share their use cases, insights and experiences with P4. The event will also feature exhibits.
In addition to live sessions, pre-recorded presentations will be released on the day of the event as well.
Check out the full agenda.

Netdev 0x16
2022-10-24 08:00
Netdev 0x16, is a conference focused on Linux kernel networking and user space utilization of the interfaces to the Linux kernel networking subsystem are the focus.
As part of this event, a hands-on workshop presented by P4 community members will take place, “Learn How to Program the Linux Kernel Data Path with P4”. The session will offer an introduction to P4 programming with available open source software. The tutorial will feature a hands-on component where participants will learn how to program custom packet processing logic into the Linux kernel through several open source P4 technologies.

Speakers:
Fernando Ramos, Associate Professor, Instituto Superior Superior Técnico, University of Lisbon
Salvatore Signorello, Invited Assistant Professor at Faculdade de Ciências da Universidade de Lisboa

Intel® 2022 P4 China Hackathon
2022-11-18 08:00
The Intel® 2022 P4 China Hackathon aims to cultivate and discover outstanding P4 talents and help developers build network infrastructure, machine learning and Applications in artificial intelligence, high-performance computing, network measurement and optimization, network security and other scenarios will enhance the innovation ability of P4 developers and promote the construction of the P4 programmable network ecosystem.

The Intel® 2022 P4 China Hackathon was initiated by Intel®, ONF community initiative, and co-organized by Jiangsu Future Network Innovation Research Institute. It is being held in conjunction with the P4 China Open Programmable Network Summit.

P4 Workshop Taiwan
2022-11-22 09:00
The P4 Workshop Taiwan is being hosted by NYCU. Industry and academia speakers with extensive P4 experience will discuss P4 use cases and academic research projects. This event is free for attendees.
09:00 – 09:10 Opening Ceremony
Jason Yi-Bing Lin, Lifetime Chair Professor (NYCU, Taiwan)
09:10 – 09:40 Keynote: Intel Tofino Expandable Architecture Platform Acceleration Kits
Daniel Alvarez, Marketing Director, Switch Fabric Group, Intel
09:40 – 10:10 Japan P4 Community Update and Use Cases
Kentaro Ebisawa, Principal Researcher, Toyota Motor Corporation
10:10 – 10:30 Break
10:30 – 11:00 P4-enabled 5G UPF QoS Enhancement and Network Slicing
Yu-Shen Liu, Accton Technology Corporation
11:00 – 11:30 Intel Infrastructure Processing Unit and IPDK Introduction
Henry Sun, Intel
11:30 – 12:00 Speeding Up Network FPGA Design Using P4
Kai-Feng Chou, Intel
12:00 – 12:10 Lunch Time (Demo)
13:10 – 13:40 P4 Testbed and Inter-Domain In-Band Telemetry
Te-Lung Liu, Research Fellow, NARLABs, Taiwan
13:40 – 14:10 Mitigating New-Flow Attack with SDN Snapshot in P4-based SDN
Meng-Hsun Tsai, Associate Professor, NCKU, Taiwan
14:10 – 14:40 Heterogeneous UPF Integration Framework and 5G User Plan Acceleration
Chien-Chao Tsent, Professor, NYCU, Taiwan
14:40 – 15:10 Break (Poster/Demo)
15:10 – 15:30 Instant Queue Occupancy Used for Automatic Traffic Scheduling in Data Center Networks
Chien Chen, Jointly Appointed Professor, NYCU, Taiwan
15:30 – 15:50 Using a P4 Hardware Switch to Block Trackers and Ads for All Devices on an Edge Network
Shie-Yuan Wang, Professor, NYCU, Taiwan
16:00 – 16:30 Intel Broadband Network Gateway Acceleration Kit (Intel BNG Acceleration Kit)
Petr Kastovsky, Software Product Manager, Intel

2022 P4 China Open Programmable Network Summit
2022-12-05 08:00
The 2022 P4 China Open Programmable Network Summit brings together experts, scholars, business executives, and technical executives to discuss the practice, development and trends of open programmable networks, P4 languages, and innovative applications of the network. Universities, research institutes and companies in the academic salon will also share P4 scientific research experiences and collaboration. In addition, the summit hosts an exhibition area.
The event is sponsored by Intel® and co-organizer, Jiangsu Future Network Innovation Research Institute.
The Intel® 2022 P4 China Hackathon will be held in conjunction with the 2022 P4 China Open Programmable Network Summit. Learn more and register separately for this event.

Euro P4 2022
2022-12-09 08:00
EuroP4 2022 took place December 9th and was held in conjunction with CoNEXT 2022 (December 6-9, 2022) in Rome, Italy.
The 5th European P4 Workshop (EuroP4) brought together networking researchers to discuss cutting-edge P4-based research and projects, P4-based tools, and the needs of the community. The workshop created an opportunity to forge connections between researchers, introduce more networking researchers to the P4 community, and seed future top-tier publications and innovation.
View proceedings from the Euro P4 Workshop.
SESSION: Security
BACKORDERS: Using Random Forests to Detect DDoS Attacks in Programmable Data Planes
Bruno Coelho (Federal University of Rio Grande do Sul (UFRGS)), Alberto Schaeffer-Filho (Federal University of Rio Grande do Sul (UFRGS)
Networks and the services they support form the communication backbone of our society, and it is important that potential Distributed Denial of Service (DDoS) attacks are detected quickly, in order to avoid or minimize the impact they may have on the availability of services. Recent technological advances in programmable networks – specifically the programmability of data planes in switches and routers, have made available new ways of detecting such attacks. By relying on this newfound possibility, this paper proposes the utilization of a Random Forest (RF) to aid in quickly and accurately detecting DDoS attacks in a programmable switch. Random forests utilize several classification trees, each of them for independently classifying an input as one of a set of classes. Here, each decision tree will classify a network flow as potentially malicious, i.e. part of a DDoS attack, or a legitimate user flow. Despite utilizing multiple classification trees to improve accuracy, random forests are relatively lightweight, with each tree requiring few and simple computations to arrive at a classification. Our results show that even small RFs, requiring as few as 63 match+action table entries, can achieve F1-Scores of over 90%.
Read Paper | View Slides

A P4-Based Content-Aware Approach to Mitigate Slow HTTP POST Attacks
Chih-Yu Hsieh (National Taiwan University), Hong-Yen Chen (National Taiwan University), Shan-Hsiang Shen (National Taiwan University of Science and Technology), Chen-Hsiang Hung (National Taiwan University), Tsung-Nan Lin (National Taiwan University)
A slow HTTP POST attack is an application-layer distributed denial-of-service attack targeting web servers. The attacker simulates a legitimate user with a slow network speed and continues to send requests, resulting in server resources being unavailable for a long time to other users. The similarity to legitimate behavior makes it challenging to identify such attack traffic. To address this issue, this paper proposes a responsive defense mechanism that exploits programmable network devices to identify attack traffic based on HTTP headers. With information that is not available from legacy network devices, this method can identify different types of requests and apply limitations. This approach achieves a distributed, source-based defense capability by utilizing data plane programmability, making it a scalable solution. The simulation results show that the approach is effective and accurate against slow HTTP POST attacks.
Read Paper | View Slides

On Implementing ChaCha on a Programmable Switch (Short Paper)
Yutaro Yoshinaka (Osaka University), Junji Takemasa (Osaka University), Yuki Koizumi (Osaka University), Toru Hasegawa (Osaka University)
This paper presents an implementation of a practical cryptographic primitive based on ChaCha on a Tofino programmable switch. A key challenge is optimizing the implementation by leveraging the structure of ChaCha operations and hardware features of Tofino. Our implementation outperforms the AES-based approach in terms of performance and small memory footprint and achieves up to 203 Gbps of throughput.
Read Paper | View Slides

SESSION: Architecture and Language
Reducing P4 Language’s Voluminosity using Higher-Level Constructs
Albert Gran Alcoz (ETH Zürich), Coralie Busse-Grawitz (ETH Zürich), Eric Marty (ETH Zürich), Laurent Vanbever (ETH Zürich)
Over the last years, P4 has positioned itself as the primary language for data-plane programming. Despite its constant evolution, the P4 language still “suffers” from one significant limitation: the voluminosity of its code. Today, P4 users overcome this limitation by relying on templating tools, hand-crafted scripts, and complicated macros. Unfortunately, these methods are not optimal: they make the development process difficult and do not generalize well beyond one codebase.
In this work, we propose reducing the voluminosity of P4 code by introducing higher-level language constructs. We present O4, an extended version of P4, that includes three such constructs: arrays (which group same-type entities together), loops (which reduce simple repetitions), and factories (which enable code parametrization).
Read Paper | View Slides
Compiling Packet Programs to dRMT Switches: Theory and Algorithms
Balázs Vass (Budapest University of Technology and Economics), Ádám Fraknói (Eötvös Loránd University), Erika Bérczi-Kovács (Eötvös Loránd University), Gábor Rétvári (Budapest University of Technology and Economics)
A critical step in P4 compilation is finding an efficient mapping of the high-level P4 source code constructs to the physical resources exposed by the underlying hardware, while meeting data and control flow dependencies in the program. In this paper, we take a new look at the algorithmic aspects of this problem, with the motivation to understand the fundamental theoretical limits and obtain better P4 pipeline embeddings in the dRMT (disaggregated Match-Action Table) switch architecture. We report mixed results. We find that optimizing P4 program embedding for maximizing throughput is computationally intractable even when some architectural constraints are relaxed, and there is no hope for a tractable approximation with arbitrary precision unless P = NP. At the same time, we find that the maximal throughput embedding is approximable in quasi-linear time with a small constant bound. Our evaluations show that the proposed algorithm outperforms the heuristics of prior work both in terms of throughput and compilation speed.
Read Paper | View Slides

In-Network Fractional Calculations using P4 for Scientific Computing Workloads
Shivam Patel (Illinois Institute of Technology), Rigden Atsatsang (Illinois Institute of Technology), Kenneth M Tichauer (Illinois Institute of Technology), Michael H L S Wang (Fermilab), James B Kowalkowski (Fermilab), Nik Sultana (Illinois Institute of Technology)
Recent P4 research has motivated the need for in-network fractional calculations to support functions in Networking (for calculations related to active queue management and load balancing) and in Machine Learning. The P4 language and ASICs do not natively support fractional types (e.g., float).

This paper re-thinks the foundation of in-network fractional calculation and proposes a new approach that is more resource conscious and is straightforward to encode in P4. Instead of floating-point, it uses a fixed-point encoding of numerals; and instead of sampling functions into tables it uses Taylor Approximation to reduce data-plane calculations to simple arithmetic over pre-calculated coefficients, requiring constant space and linear time. The paper describes and evaluates a P4 code synthesis algorithm that allows users to trade-off switch resources for accuracy, grounded on an application of a well-understood mathematical theory. It describes how to encode π and various functions including cos, log and exp.
Read Paper
HOL4P4: Semantics for a Verified Data Plane
Anoud Alshnakat (KTH Royal Institute of Technology), Didrik Lundberg (KTH Royal Institute of Technology, Saab AB), Roberto Guanciale (KTH Royal Institute of Technology), Mads Dam (KTH Royal Institute of Technology), Karl Palmskog (KTH Royal Institute of Technology)
We introduce a formal semantics of P4 for the HOL4 interactive theorem prover. We exploit properties of the language, like the absence of call by reference and the copy-in/copy-out mechanism, to define a heapless small-step semantics that is abstract enough to simplify verification, but that covers the main aspects of the language: interaction with the architecture via externs, table match, and parsers. Our formalization is written in the Ott metalanguage, which allows us to export definitions to multiple interactive theorem provers. The exported HOL4 semantics allows us to establish machine-checkable proofs regarding the semantics, properties of P4 programs, and soundness of analysis tools.
Read Paper | View Slides

SESSION: Monitoring and Applications
Causal Network Telemetry

Yunhe Liu (Cornell University), Nate Foster (Cornell University), Fred B. Schneider (Cornell University)
Current approaches to network observability rely on techniques like active probing, packet sampling, and path-level telemetry, which only provide a partial view. This paper presents causal telemetry, a new model that adapts ideas from distributed systems to the network setting. Causal telemetry captures causal relationships between events, including those that take place on physically separated devices. We motivate causal telemetry through examples, we show how it can be used to diagnose anomalies and faults, and we present algorithms for constructing the needed causal graphs from network executions. We develop a P4-based prototype implementation, CoCaTel, and discuss a case study that uses causal telemetry to detect Priority-Based Flow Control (PFC) deadlocks.
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Innovative network monitoring techniques through In-band Inter Packet Gap Telemetry (IPGNET)
Francisco Germano Vogt (University of Campinas), Fabricio Rodriguez (University of Campinas), Christian Esteve Rothenberg (University of Campinas), Gergely Pongrácz (Ericsson Research)
Network monitoring is a fundamental task for proper network troubleshooting and performance management. Recently, in-band Network Telemetry (INT) has been demonstrated as a powerful and efficient network monitoring framework. Using INT, network information hop-by-hop can be collected directly from the data plane by gathering this information in the production traffic. However, INT data collection is limited by available packet size and processing overhead, making it critical to choose what data to collect and when to collect it. In this demo, we propose the In-band Inter Packet Gap Network Telemetry (IPGNET) per-hop monitoring. We argue that by monitoring the IPG hop-by-hop, it is possible to correlate the data and identify: (i) Network problems like congestion and delays, finding their root cause, and (ii) Microbursts and their contributing flows. Our preliminary results show that IPGNET can detect microbursts on multiple queues and report all the contributing flows with high efficiency in terms of control/data plane overhead.

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Sketch-based Entropy Estimation: a Tabular Interpolation Approach Using P4 (Short Paper)
Yu-Kuen Lai (Chung-Yuan Christian University), Se-Young Yu (International Center for Advanced Internet Research), Iek-Seng Chan (Chung-Yuan Christian University), Bo-Hsun Huang (Chung-Yuan Christian University), Che-Hao Chang (National Taiwan University), Jim Hao Chen (International Center for Advanced Internet Research), Joe Mambretti (International Center for Advanced Internet Research)
This work presents the implementation of a tabular interpolation approach to estimate empirical Shannon entropy on programmable data plane ASICs using P4. The technique transforms the complex computations of the random projection into fast lookup over pre-computed tables in the match-action pipeline. Likewise, the interpolation heuristic further reduces the table size substantially. Thus, more tables can be accommodated, achieving higher estimation accuracy. Simulations based on real-world network traffic traces are performed to evaluate the estimation accuracy. The scheme is deployed in a Barefoot Tofino2 switch connected to the International Center for Advanced Internet Research (iCAIR) national testbed. The system can estimate the entropy of network traffic accurately at 400 Gbps throughput.
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In-network Angle Approximation for Supporting Adaptive Beamforming
Hiba Mallouhi (ELTE Eötvös Loránd University, Budapest, Hungary), Jaspreet Kaur (University of Glasgow), Hasan Tahir Abbas (University of Glasgow), Sándor Laki (ELTE Eötvös Loránd University, Budapest, Hungary)
Beamforming is now an integral feature of modern wireless communication systems and its implementation calls for an accurate beam alignment by estimating the direction of signal arrival. However, this estimation is computationally complex, especially in a dynamic environment where a user is constantly on the move. In this paper, we propose a user-assisted in-network method to optimally approximate the angle of arrival by segmenting the cell area into an exponentially binned grid and make use of the advantages offered by programmable data planes and their match-action table (MAT) logic. The proposed method is implemented in P4 and runs on a Tofino ASIC. Our evaluation proves a theoretical bound on the absolute error of the proposed MAT-based angle approximation and shows that it is in accordance with the empirical error distributions.

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Distributed DNN Serving in the Network Data Plane
Kamran Razavi (Technical University of Darmstadt), George Karlos (Vrije Universiteit Amsterdam), Vinod Nigade (Vrije Universiteit Amsterdam), Max Mülhäuser (Technische Universität Darmstadt), Lin Wang (Technische Universität Darmstadt, Vrije Universiteit Amsterdam)
There is a great interest in utilizing P4 for in-network computing along with programmable data planes. This use is emerging as a new network paradigm that can not just reduce the complexity but the delay as well. Beamforming is now an integral feature of modern wireless communication systems and its implementation calls for an accurate beam alignment by estimating the direction of signal arrival. However, this estimation is computationally complex, especially in a dynamic environment where a user is constantly on the move.
In this paper, we propose a user-assisted in-network method to optimally approximate the angle of arrival by segmenting the cell area into an exponentially binned grid and make use of the advantages offered by programmable data planes and their match-action table (MAT) logic. The method expects location messages periodically reported by user equipment, processes them in the network and reconfigures the base station antennas accordingly, implementing user-assisted in-network beam control. The proposed method is implemented in P4 and runs on a Tofino ASIC.
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Organizer Co-Chairs

Gianni Antichi, Queen Mary University of London
Fernando Ramos, University of Lisbon

TPC Co-Chairs

Marco Chiesa, KTH Royal Institute of Technology
Shir Landau Feibish, Open University of Israel

Publicity Chair

Marco Savi, University of Milano-Bicocca

Program Committee

Alan Zaoxing Liu (Boston University)
Amedeo Sapio (Intel)
Ben Pfaff (VMware)
Daehyeok Kim (Microsoft Research)
Damu Ding (University of Oxford)
Gábor Rétvári (Budapest University of Technology and Economics)
Hyojoon Kim (Princeton University)
Mihai Budiu (VMware Research)
Mina Tahmasbi Arashloo (University of Waterloo)
Muhammad Shahbaz (Purdue University)
Ori Rottenstreich (Technion)
Roberto Bifulco (NEC Laboratories Europe)
Salvatore Signorello (University of Lisbon)
Sándor Laki (Eötvös Loránd University)
Simone Ferlin (Red Hat, Karlstad university)

2023 APRICOT APNIC 55
2023-02-20 14:30 - 2023-03-02 16:00
March 1st | 2:30 – 4:00 pm | Visayas Ballroom
View Video (1:29)
Check out this insightful tutorial, “P4 Programming Protocol-Independent Packet Processor”, now on-demand, by ONF Ambassador and National University of Singapore (NAS) Research Fellow, Aris Cahyadi Risdianto. In his talk he provides an introduction to P4 and data plane programmability using the P4 programming language, concluding with a demo on programming a switch using P4.

FOSSASIA Summit 2023
2023-04-14 11:15
April 14th | 11:15 am SGT
Aris Cahyadi Risdianto, ONF Ambassador and Research Fellow, National University of Singapore, presented “Develop and Verify Networking Program with P4 and Mininet,” at FOSSASIA Summit 2023.
Abstract: P4 (programming protocol-independent packet processors) is a special language to define how the network packet forwarding process is built independently from the underlying hardware. It can be used to dynamically reconfigure the forwarding process on the different target hardware, such as ASIC, FPGA, or SmartNIC. Users can write complete networking programs that includes in-band telemetry/measurement, traffic load-balancing, anti-DDoS, packet broker, and offload protocols. The program can be tested using widely available network emulator, called Mininet, so that the behavior of packet forwarding can be verified before it is deployed in the real target hardware. In this presentation, we will quickly go through on how the P4 program looks like, how to compile, and how it is verified using Mininet emulator software.

2023 P4 Workshop
2023-04-24 08:00 - 2023-04-25 08:00
The P4 Workshop is an opportunity for the P4 ecosystem to share knowledge and experiences with the broader community and to facilitate collaboration. The workshop incorporates insights and perspectives from the P4 community across the following key areas:

P4 language
P4 targets
P4 tool chain
P4 use cases & applications
Control plane or network OS for P4 targets
Extensions to P4
Cross-cutting work between P4 and related systems such as eBPF and service meshes.

View individual videos and slides below! Or, view YouTube playlist.
Keynotes

Title
Video
Slides

Welcome & State of P4
Mina Tahmasbi Arashloo, Program Chair, University of Waterloo
Andy Fingerhut, Principal Engineer, Intel

Fireside Chat with Nick McKeown
Nick McKeown, P4 Co-founder & Evangelist
Larry Peterson, Chief Scientist, ONF

Developing Real World Applications Using P4-Based Architecture
Krishna Doddapaneni, Corporate Vice President, AMD Pensando

P4 HAL for Network Virtualization
Parveen Patel, Google Cloud, Senior Director Engineering, Google Cloud

The Power of Fully-Specified Data Planes
Rob Sherwood, Chief Technology Officer, NEX Cloud Networking Group, Intel

From Programmability to Fungibility
Ang Chen, Assistant Professor Computer Science, Rice University

Can SmartNICs Help Accelerate Distributed Systems?
Arvind Krishnamurthy, Short-Dooley Professor, Paul G. Allen School of Computer Science & Engineering, University of Washington

In-Depth Talks

Title
Video

Slides

Escaping Babel: The Flow Must Go On
Victor Rios, Google

OpenConfig Co-Existence with P4 Using TDI
James Choi, Cloud SW Architect, Intel

Formalizing and Extending P4’s Type System
Parisa Ataei, Postdoc, Cornell University

Effective DGA Family Classification Using a Hybrid Shallow and Deep Packet Inspection Technique on P4 Programmable Switches
Ali AlSabeh, University of South Carolina

Segment Routing Proxy Device implemented Using P4 on FPGA with Zero CPU Overhead
Miroslaw Walukiewicz, Intel

Hardware Offload Driver with P4-TC
Anjali Singhai Jain, Network Architect, Intel
Namrata Limaye, Intel

P4TC: Linux Kernel P4 implementation Approaches and Evaluation
Deb Chatterjee, Intel
Jamal Hadi Salim, Mojatatu Networks

Augmenting P4-DPDK Software Pipelines with Accelerators: the IPsec Use Case
Andy Fingerhut, Intel

Lightning Talks

Title
Video

Slides

Intent-based Platform Leverages Programmable Networking for Optimizing Edge
Dave Duggal, Founder/CEO, EnterpriseWeb
William Malyk, Chief System Architect, EnterpriseWeb

A Language Engineering Approach to Support the P4 Coding Ecosystem
Alexandre Lachance, Graduate Student, McMaster University

Enhancing Blockage Detection and Handover on 60 GHz Networks with P4 Programmable Data Planes
Ali AlSabeh, Computer Science PhD Student, University of South Carolina

P4MS: Leveraging Passive Measurements from P4 Switches to Dynamically Modify a Router’s Buffer Size
Jose Gomez, Graduate Assistant, University of South Carolina

P4 Working Group Update

Title
Video

Slides

What’s New in P4-16
Mihai Budiu, P4 Language Design Working Group Co-Chair

P4.org Architecture Work Group
Mario Baldi, P4 Architecture Working Group Co-Chair
Andy Fingerhut, P4 Architecture Working Group Co-Chair

P4 API Working Group Annual Wrap-up
Chris Sommers, API Working Group Co-Chair
Steffen Smolka, API Working Group Co-Chair

Demos

Title
Video

Slides

A Language Engineering Approach to Support the P4 Coding Ecosystem
Alexandre Lachance, Graduate Student, McMaster University

Demo to Offload Networking Pipeline on Intel IPU E2000 Using P4 Control Plane
Nupur Uttarwar, Cloud Software Engineer, Intel
Namrata Limaye, Senior Engineering Manager, Cloud Software, Intel

Enabling P4 hands-on Training Using Hardware Switches in a Cloud System at the University of South Carolina
Jose Gomez, Graduate Assistant, University of South Carolina

Enhancing Blockage Detection andHandover on 60 GHz Networks with P4 Programmable Data Planes
Ali AlSabeh, Research Assistant, University of South Carolina

Posters

Title
Details

A Testbench for Testing Programmable Traffic Managers in a Software Environment
Bill Pontikakis, Research Associate, Polytechnique Montreal

Casual Network Telemetry
Yunhe Liu, Research Assistant, Cornell University

Enhancing Blockage Detection and Handover on 60 GHz Networks with P4 Programmable Data Planes
Ali AlSabeh, Research Assistant, University of South Carolina

Extending the P4 Language to Facilitate the Use of Stateful Constructs
Jorg Ehmer, Polytechnique Montreal

Intent-based Platform Leverages Programmable Networking for Optimizing Edge
Dave Duggal, Founder/CEO, EnterpriseWeb
William Malyk, Chief System Architect, EnterpriseWeb

Euro P4 2023
2023-12-08 08:00
EuroP4 2023 took place December 8th in conjunction with ACM CoNEXT 2023 in Paris (France). This event brought together networking researchers and practitioners to discuss cutting-edge, P4-enabled research and P4-based technology. The workshop provided a venue for presenting and discussing research and projects related to P4, as well as for more broadly discussing the needs of this research community. The workshop aimed to forge new connections between researchers who already work with P4, introduce more networking researchers to the P4 community, and seed future top-tier publications, innovation and contributions to this community.
View proceedings from the 2023 EuroP4 Workshop

Session 1: P4 Networking

LANTERN: Layered Adaptive Network Telemetry Collection for Programmable Data Planes
Kaiyu Hou (Alibaba Cloud), Dhiraj Saharia (Georgetown University), Vinod Yegneswaran (SRI International), Phil Porras (SRI International)

Abstract:
Managing next-generation enterprise networks requires collecting and analyzing enormous volumes (tens of Tbps) of network traffic data in real time to detect potential anomalies, classify attacks, identify root causes, and rapidly deploy effective mitigations. Conducting robust and scalable analysis on such traffic volumes is a daunting ”haystack” problem that demands intelligent strategies to winnow traffic to extract and pinpoint ”needles” of interest. Recent advances in software-defined networking and programmable dataplanes, that enable dynamic reconfiguration of switching hardware to adapt to changing traffic conditions, provide a foundational building block. However, they lack the resources and programming primitives for complex computational models.
Toward that end, we present LANTERN, a layered and adaptive network telemetry system that facilitates joint collection and analysis of network traffic at multiple resolutions in coordination with the controller. Our design offloads complex machine-learning analysis to the controller, while still enabling proactive telemetry refinement and reactive mitigation triggers at the data-plane level. We evaluate our layered approach by replaying a labeled CIC-IDS attack dataset through both software and hardware P4 switches. LANTERN is able to detect most anomalies, accurately classify them, and introduces negligible switching overhead (1% latency).
Read Paper | View Slides

Per Priority Data Rate Measurement in Data Plane
Habib Mostafaei (Eindhoven University of Technology), Georgios Smaragdakis (Delft University of Technology)
Abstract:
Many applications, such as video streaming, congestion control, and server selection, can benefit when the data rate of different priority groups between two endpoints is accurately estimated over the end-to-end path. With the introduction of programmable networks, e.g., P4, it is now possible to offload the measurements to the data plane of intermediate devices. Recently, tools have been developed to react to changes in available bandwidth, but a tool to accurately estimate end-to-end per-priority data rates needs to be added. This motivates us to design and implement a new end-to-end and per-priority data rate estimation tool, PrioMeter. PrioMeter can accurately report the data rate per priority group of flows in programmable networks using high-precision timestamps for arbitrary traffic scales. PrioMeter leverages two primitives: quantization and truncation, to achieve its goals. We implement PrioMeter in P4 and test it on BMv2 switches, and our preliminary results using NS3 simulations show that it can accurately estimate the data rate of different priority flows with minimal overhead.
Read Paper | View Slides

Cryptographic Path Validation for SCION in P4
Lars-Christian Schulz (OVGU Magdeburg), Robin Wehner (OVGU Magdeburg), David Hausheer (OVGU Magdeburg)
Abstract:
SCION has been proposed as a new Internet architecture addressing security and scalability shortcomings in the current Internet. Multiple real-world deployments of SCION exist already, nevertheless few hardware implementations of SCION routers are available.
In this paper, we implement a SCION border router on a programmable 12.8 Tbit/s Intel Tofino 2 switch. Our router utilizes the multiple separately programmable packet pipelines of Tofino 2 in order to compute SCION’s AES-CMAC-based hop authenticators in general-purpose P4 without assistance from specialized hardware.
Using three out of four available pipelines, we achieve 394.7 Gbit/s throughput per port on 8 ports for a total of 3.16 Tbit/s capacity. Using only two pipelines we still achieve line rate throughput on 4 ports for a total of 1.58 Tbit/s capacity. To our knowledge there is no other SCION router including the AES-CMAC validation that offers a comparable performance.
Read Paper | View Slides

Session 2 – P4 Control & Targets

Introducing P4TC – A P4 Implementation on Linux Kernel using Traffic Control
Jamal Hadi Salim (Mojatatu Networks), Deb Chatterjee (Intel Corporation), Victor Nogueira (Mojatatu Networks), Pedro Tammela (Mojatatu Networks), Tomasz Osinski (Intel Corporation), Evangelos Haleplidis (Mojatatu Networks), Balachandher Sambasivam (Intel Corporation), Usha Gupta (Intel Corporation), Komal Jain (Intel Corporation), Sosutha Sethuramapandian (Intel Corporation)
Abstract:
The networking industry is at an inflection point with ever increasing network link capacities coupled with the presence of programmable hardware ASICs. These set of circumstances call out for a robust approach to hardware and software co-existence for network programmability.
P4TC is a P4 Linux kernel-native implementation on top of the Linux Traffic Control (TC) infrastructure that provides a vendor-neutral, kernel-independent and architecture-independent interface for Match-Action packet processing compatible with the P4 specification. P4TC facilitates both a hardware datapath and a functionally equivalent kernel eBPF-assisted software datapath making it ideal to deal with both high speed links and programmable hardware.
In this paper, we describe the goals and motivation of P4TC, the design and architecture as well as illustrate the different concepts of the P4TC infrastructure via an example of a simple L2 switch.
Read Paper | View Slides

NAP: Programming data planes with Approximate Data Structures
Mengying Pan (Princeton University), Hyojoon Kim (University of Virginia), Jennifer Rexford (Princeton University), David Walker (Princeton University)
Abstract:
Many applications that run on programmable data planes rely on approximate data structures, due to insufficient in-network memory. However, programming with approximate data structures is challenging because it requires (1) expertise in streaming algorithms to select the data structures that best match an application’s requirements, (2) meticulous configuration to minimize approximation error while fitting within the hardware constraints, and (3) proficiency in the low-level P4 language. To address these issues, we propose NAP, a high-level network programming language. The core of NAP is the versatile approximate dictionary abstraction that captures a wide range of compact data structures, while allowing programmers to simply specify the kinds of error an application can tolerate. We demonstrate the language’s expressiveness, conciseness, and efficiency through a variety of network applications, each compiling to P4 for the Intel Tofino in less than a second and featuring 25X–50X fewer lines of code compared to the P4 output. We evaluate an approximate stateful firewall written in NAP with real campus traffic, achieving performance consistent with the predicted accuracy.
Read Paper | View Slides

P4EAD: Securing the In-band Control Channels on Commodity Programmable Switches
Archit Bhatnagar (Birla Institute of Technology & Science, Pilani), Xin Zhe Khooi (National University of Singapore), Cha Hwan Song (National University of Singapore), Mun Choon Chan (National University of Singapore)
Abstract:
Conventionally, the control channel on network switches has always been out-of-band. With the emergence of high-performance systems built upon programmable switches, the out-of-band control channel has become the bottleneck. Thus, there is an emerging trend of implementing the control channel in the data path (i.e., in-band) on programmable switches to achieve high throughput and low-latency control actions. However, the use of in-band control channels comes with the risk of security vulnerabilities that have not been explored in prior literature. In this paper, we present P4EAD, a cryptographic primitive to secure the in-band control channels on programmable switches entirely in the data plane. This ensures the integrity, authenticity, and confidentiality of in-band control messages. We conduct micro-benchmarks on P4EAD and demonstrate its integration with an existing high-performance in-band control framework, showcasing minimal performance impact when securing the control channel.
Read Paper | View Slides

Posters and Demos Session
Poster: High-Speed Per-Packet Checksums on the Intel Tofino
David Grölle (OVGU Magdeburg), Lars-Christian Schulz (OVGU Magdeburg), Robin Wehner (OVGU Magdeburg), David Hausheer (OVGU Magdeburg)
Abstract:
Path-aware networking has introduced new possibilities to monitor and control network access and solved a multitude of modern-day Internet security issues. Being able to authorize usage of specific paths enables network operators to offer high-quality services to customers requiring highly reliable network access.
Currently, securing a network path or an end host is only possible by using high-level solutions like VPNs. With EPIC-HP (Every Packet Is Checked – Hidden Path), it has been shown that it is possible to move this functionality down into the network itself. EPIC-HP extends the path-aware Internet architecture SCION by offering per-packet checksums, adding authentication to network traffic. This is used to combat DoS attacks on the network’s end hosts and give high-priority access to specific end users. In this paper, we show that it is possible to implement the functionality of EPIC-HP along with SCION on the Intel Tofino 2 ASIC. EPIC-HP requires AES-based MAC verification with per-path keys in the data plane. By using the multi-pipeline structure of the Tofino, we implemented the required AES and AES-CMAC cryptography using three pipes of the switch’s total four independent pipes.
The throughput we achieve is an order of magnitude above the data rates previously achieved for EPIC-HP and is a significant step towards a more secure Internet.
Read Paper

Poster: P4DME: DNS Threat Mitigation with P4 In-Network Machine Learning Offload
Juan Vanerio (University of Vienna), Csaba Györgyi (University of Vienna), Stefan Schmid (TU Berlin, Fraunhofer SIT)
Abstract:
The ever-evolving cybersecurity landscape demands innovative solutions to safeguard critical network infrastructure such as the Domain Name System (DNS). This paper presents P4DME, a novel approach that harnesses the potential of Machine Learning (ML) in conjunction with P4 programmable switches to tackle DNS threats efficiently. P4DME’s primary benefit lies in offloading filtering from resource-intensive ML processing tasks on dedicated servers. This offloading boosts the overall traffic throughput that can be inspected or achieves the same throughput with reduced resource consumption while preserving the servers’ capabilities for high-performance threat identification. This work uses P4-based in-network elements to handle crucial DNS threats, dynamic white- and blacklisting, and an online popularity-based anomaly detection heuristic. The latter serves as a trigger for dedicated ML-based inspection. Furthermore, we introduce in-network mitigation filters updated through the control plane to provide adaptable and responsive threat mitigation. Preliminary simulation results show more than 99.9% offload ratio at 5% increased False Negative Ratio.
Read Paper

Poster: Maintaining Sets With Deletions in the Data Plane
Jonathan Diamant (The Open University of Israel), Shir Landau Feibish (The Open University of Israel)
Abstract:
Sets are one of the most fundamental data types in Computer Science, and data structures used to maintain sets are used in many algorithms. These structures normally support three basic operations: insertion, look-up (i.e. set-membership query), and deletion. The most common set-membership data structure used in the data plane is the Bloom Filter (BF). While BFs are relatively easy to adapt to the data plane, they offer a limited set-membership functionality as they do not support deletions. If deletions are required, a Counting Bloom Filter (CBF) (which maintains counters instead of bits) may be used. Yet, if a key was inserted multiple times, multiple deletions would be needed to completely remove the key from the structure. We present MEM-D, a fast and lightweight set-membership data structure for the data plane, which supports all three operations: look-up, insertion, and deletion. MEM-D supports the uniqueness property, meaning that a key would be removed with a single deletion operation even if it was inserted multiple times. MEM-D provides a false positive (FP) error rate similar to the rate of the standard BF and additionally may incur a small false negative (FN) error. We have implemented MEM-D on a hardware Tofino target using P4. To the best of our knowledge, MEM-D is the first data structure for set-membership in the data plane, which supports deletion.
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Poster: Adaptive In-Network Inference using Early-Exits
Heewon Kim (Korea University), Seongyeon Yoon (Korea University), Sangheon Pack (Korea University)
Abstract:
In-network (or on-path) inference over programmable data planes allows fast and low-overhead inference in deep neural networks. In this work, we propose an adaptive approach to strike the balance between accuracy and processing cost. To be specific, the confidence score is evaluated at the end of each layer, and an early exit is triggered if the confidence score is sufficiently high. We implement this early-exit scheme over BMv2 software switches and the results demonstrate that the proposed scheme successfully controls the trade-off by making use of the confidence score.
Read Paper

Demo: Enabling DNN-Based Inference in the Network Data Plane
Siddhartha (AMD), Justin Tan (AMD & NUS), Rajesh Bansal (AMD), Chee Chung Chan (AMD), Yuta Tokusashi (AMD), Yew Kwan Chong (AMD), Haris Javaid (AMD), Mario Baldi (AMD)
Abstract:
Advancements in programmable packet processing technologies have fostered innovation across a range of networking applications. Integration of deep neural networks (DNN) in the network data plane, however, has remained largely unaddressed due to the high compute requirements of the underlying algebraic kernels. In this paper, we show how P4 packet processing pipelines can be augmented with DNN inference engines on devices readily available in the market today. We share a network security case study, where we train a DNN-based anomaly detector that classifies active traffic flows as either malicious or benign using per-packet inference. Our implementation runs on an AMD AlveotextsuperscriptTM U250 FPGA accelerator card, and is capable of servicing network traffic of up to approx~98~Mpps on 100~GbpE links.
Read Paper

Workshop General Chairs
Fernando Ramos, University of Lisbon
Muhammad Shahbaz, Purdue University
Program Chairs
Vladimir Gurevich, P4ica
Salvatore Signorello, Telefonica Research, Spain
Publicity Chairs
Denise Barton, ONF
Sandor Laki, Eötvös Loránd University
Program Committee
Alan Lo, NVIDIA
Alan Zaoxing Liu, University of Maryland
Andy Fingerhut, Intel
Anirudh Sivaraman, New York University
Christian Esteve Rothenberg, University of Campinas
Daehyeok Kim, University of Texas at Austin
Davide Sanvito, NEC Labs
Ennan Zhai, Alibaba Cloud
Gianni Antichi, Politecnico di Milano & Queen Mary University of London
Jiarong Xing, Rice University
Mario Baldi, AMD & Politecnico di Torino
Nate Foster, Cornell University
Nik Sultana, Illinois Institute of Technology
Robert Soulé, Yale University
Shir Landau Feibish – The Open University of Israel

P4 Open Source Developer Days: P4 Traffic Generator and Analyzer
2024-04-02 08:00
April 2nd 2024
In case you missed it, you can now watch the recording of the recent P4 Developer Days Talk by Steffen Lindner (University of Tuebingen) on the P4TG traffic generator and analyzer.
“We present P4TG, an open-source P4-based traffic generator (TG) which runs on the programmable Intel Tofino ASIC. In generation mode, P4TG is capable of generating traffic up to 1 Tb/s split across 10x 100 Gb/s ports. Thereby it measures rates directly in the data plane. Generated traffic may be fed back from the output to the input ports, possibly through other equipment, to record packet loss, packet reordering, inter-arrival times (IATs) and sampled round trip times (RTTs). Further, it supports VLAN, QinQ, and MPLS encapsulation. In analysis mode, P4TG measures rates on the input ports and IATs, and forwards traffic through its output ports. Existing software or P4-based traffic generators either lack the required accuracy, do not support high data rates, or do not provide sufficiently integrated measurement capabilities.”

ONE Summit 2024: P4-Based Automated Reasoning
2024-04-29 08:00 - 2024-05-01 08:00
Check out the video and slides by P4 TST member Steffen Smolka, “P4-based Automated Reasoning” which was featured at The Linux Foundation’s One Summit 2024. In his talk he discusses how P4 is now being used as a specification language for network programmable and non-programmable pipelines. He discusses how Google and others have been leveraging such machine-readable, unambiguous, vendor-agnostic specifications of their switches to increase network reliability and development as well as allow the SDN controller to interoperate seamlessly with switches form different vendors.

View Video
Review Slides

2024 P4 GSoC Projects - Webinar
2024-09-05 09:00
Thursday, September 5, 2024
9:00am Pacific
View Video
Learn about the four exciting projects hosted by the P4 Language Organization as part of Google‘s Summer of Code (GSoC) 2024. Each of the project contributors present their projects followed by a short discussion.
P4 Projects in GSoC

View Project Details
Improving the documentation of the P4 Compiler
Contributor: Adarsh Rawat, Graphic Era Deemed to be University
Mentors: Fabian Ruffy, Davide Scano
Building a Formatter for the P4 Language
Contributor: Nitish Kumar, Indian Institute of Technology Kharagpur
Mentors: Bili Dong, Fabian Ruffy
Introducing PNA support to BMv2
Contributor: Rupesh Chiluka, University of Hyderabad (UoH)
Mentors: Hari Thantry, Debobroto Das Robin
P4-Enabled Container Migration in Kubernetes
Contributor – Stanislav Korosin, Technische Universität Berlin
Mentors: Davide Scano, Radostin Stoyanov

2024 P4 Workshop
2024-10-03 08:00
The 2024 P4 Workshop took place October 3rd, and was hosted and sponsored by Google. This in-person event took place at Google’s Moffett Park Campus in Sunnyvale, California and offered an opportunity for the P4 ecosystem to share knowledge and experiences with the broader community and to facilitate collaboration.
View individual videos and slides on-demand from the event below! Or, view YouTube Playlist.
Invited Talks

Title
Video
Slides

Welcome, State of P4 & 2024 Distinguished Contributor Award
Andy Fingerhut, Principal Engineer, Intel

Keynote – Navigating Internet Research with P4: Solutions for Performance and Security
Maria Apostolaki, Assistant Professor of Electrical and Computer Engineering, Princeton University

Fireside Chat with Martin Casado
Martin Casado, General Partner, Andreessen Horowitz
Nate Foster, Professor Computer Science, Cornell University

P4 on Hardware: The Future
Konstantin Weitz, Staff Software Engineer, Google (Moderator)
Vipin Jain, Sr Fellow Engineer, AMD
Anjali Singhai Jain, Network Architect, Intel

In-Depth Talks

Title
Video

Slides

Past, Present and Future of P4
Deb Chatterjee, Sr Director Software Engineering, Intel

Compiler-assisted Kernel-based P4 Pipeline Offloading Using Intel IPU
Deb Chatterjee, Sr Director Software Engineering, Intel
Neha Singh, Staff Software Engineer, Intel

Towards the Performant P4C
Anton Korobeynikov, Principal Software Engineer, Compiler Development, Access Softek Toolchains

Supporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme
Bill Pontikakis, Sr Research Associate, Polytechnique Montréal
François-Raymond Boyer, Professeur, Polytechnique Montréal

SONiC DASH on Intel IPU2100
Shweta Shrivastava, Cloud Software Engineer, Intel
Namrata Limaye, Director Software Engineering, Intel

Internals of the Intel Tofino Compiler
Glen Gibb, Compiler Engineer, Intel

P4-SpecTec – Mechanized Language Definition for P4
Jaehyun Lee, Student, KAIST

Centralized Telemetry and Security Enforcement Using SONiC and P4
Shekher Bulusu, Sr Manager Software Engineering, GEICO
Pawan Ravi, Sr Staff Engineer, GEICO
James Choi, Sr Engineering Manager, GEICO

Modeling Hardware Blocks of Network ASICs using P4
Jean Tourrilhes, Researcher, HPE

In-Memory Key-Value Store Live Migration with NetMigrate
Zeying Zhu, PhD Student, University of Maryland

P4-Based Automated Reasoning (P4-BAR) for the (Networking) Masses!
Steffen Smolka, Staff Software Engineer, Google
Jonathan DiLorenzo, Software Engineer, Google

Scaling P4-Based Automated Reasoning (Performance and Coverage)
Ali Kheradmand, Senior Software Engineer, Google
Meghana Sistla, PhD Student, University of Texas at Austin

P4HIR: Toward Bridging P4C with MLIR
Bili Dong, Software Engineer, Google

Demos

Title

Abstract

SONiC DASH on Intel IPU2100
Namrata Limaye, Director Software Engineering, Intel

Data Center Routing GEICO SDN Controller and GEICO SONiC Using P4
Sunil Kumar Rawookar, Staff Engineer, GEICO Tech

Offload NAT and Routing onto Intel IPU Using P4-TC
Neha Singh, Staff Software Engineer, Intel

P4 IDE: An Integrated Development Environment for P4-based Data Plane Development
Namrata Limaye, Director Software Engineer, Intel

P4Docker: Simplifying P4 Switch Testbeds with Docker Integration
Lucas Trombeta, PhD Candidate, Federal University of ABC (UFABC)

Supporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme
Bill Pontikakis, Sr Research Associate, Polytechnique Montréal
François-Raymond Boyer, Professeur, Polytechnique Montréal

Poster

Title
Abstract

Babel: The Tower So Far
Victor Rios, Software Engineer, Google

General Chair – Nate Foster
Program Co-Chairs – Andy Fingerhut, Muhammad Shahbaz
Program Committee
– Jehandad Khan, AMD
– Ori Rottenstreich, Technion
– Vishal Shrivastav, Purdue University
– Gianni Antichi, Politecnico di Milano and Queen Mary University of London
– Ben Pfaff, Feldera
– Ajay Lotan Thakur, Intel Corp
– Victor Liu, University of Michigan
– Vladimir Gurevich, P4ica
– Tushar Swamy, unaffiliated
– Yiming Qiu, University of Michigan
– Amedeo Sapio, Amazon Web Services
– Lavanya Jose, Google

Japan P4 Users Group
2024-10-25 08:00
The 2024 Japan P4 Users Group was hosted as a hybrid in-person and online event and included P4-related presentations and exhibits. View the agenda and resources. Talks were presented in Japanese and video can be accessed here.

P4 Developer Days - P4 in SDN-based Attack Detection and AI-driven Security Mechanisms
2025-05-06 08:00
May 6, 2025 | 8:00am Pacific
View Video
View Slides
Abstract
Software-Defined Networking (SDN) is a promising network architecture that offers greater flexibility and scalability compared to traditional network infrastructures. This flexibility arises from the separation of the data plane from the control plane, which enables the use of general-purpose devices, commonly referred to as “dumb devices” in SDN. While this separation enhances network management and administration, it also imposes processing limitations, leading to increased overhead on the controller. This is precisely where P4, a domain-specific programming language for packet processing, becomes highly beneficial.
In the field of network security, particularly in attack detection, researchers have proposed various innovative methods. P4 can play a crucial role in advancing these solutions by leveraging a programmable data plane to offload processing tasks from the controller, thereby achieving a more balanced distribution of computational load between the data and control planes. One of the most critical areas of application in this regard is the detection and mitigation of Distributed Denial-of-Service (DDoS) attacks.
Additionally, there has been a significant rise in AI-based security solutions, with machine learning (ML) being a prominent subfield. ML enables the development of custom AI agents tailored for specific tasks, requiring the extraction of relevant features for training purposes. However, without a programmable data plane, this approach is impractical in both SDN and traditional networks. With P4, however, such implementations become feasible, opening new possibilities for AI-driven network security solutions.
In this webinar, we will explore the use cases of P4 in SDN-based attack detection and AI-driven security mechanisms, highlighting its potential to enhance modern network security strategies.
Speaker
Reza Fallahi Kapourchali holds an M.Sc. in Computer Networks from Bu-Ali Sina University, Hamedan, Iran. His research interests encompass a broad spectrum of critical areas, including computer network security, P4 technology, wireless networks, 5G networks, the Industrial Internet of Things (IIoT), and network Quality of Service (QoS). His commitment to advancing innovation and knowledge in these fields is evidenced by his published articles, which contribute to the development of secure and efficient network architectures.
