P4 Developer Days – A Multi-Site Testbed for Heterogeneous P4 Data Plane Experimentation on Research Cyberinfrastructure
2026-06-10 08:00 - 09:00 (America/Vancouver)
Register to attend this P4 Developer Day webinar on June 10 at 11 am ET/5 pm CET
Slides (PDF) | Watch Recording
A Multi-Site Testbed for Heterogeneous P4 Data Plane Experimentation on Research Cyberinfrastructure

Abstract
This presentation introduces a multi-site testbed that unifies three distinct classes of P4-programmable hardware, FPGA SmartNICs (AMD Alveo), DPUs (NVIDIA BlueField), and software switches (BMv2), under a single Kubernetes control plane on the National Research Platform (NRP). We detail the architecture that uses ESnet’s SENSE orchestrator for dynamic multi-domain Layer 2 path provisioning and a unified shell automation framework for reproducible experiments. We also share critical lessons learned from integrating heterogeneous targets and running a real-world deployment. This work provides a blueprint for building and operating advanced, reproducible P4 experimentation infrastructure for the research community.
Speaker
Mohammad Firas Sada is a researcher at SDSC specializing in deep learning, high-performance computing (HPC), and advanced networking. His work within the Nautilus Kubernetes cluster at the National Research Platform focuses on distributed AI workflows, network programmability, hardware acceleration with novel compute architectures, and scalable cyberinfrastructure for data-intensive science. His interests include optimizing AI training across GPU clusters, accelerating scientific computing with programmable networks, and developing tools for large-scale data movement and workflow automation. He enjoys working with talented teams to foster collaboration, exchange ideas, and advance research in computing.

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P4 GSoC 2026 || Kickoff Meeting
2026-06-12 07:00 - 08:30 UTC
Join us for the 2026 P4 GSoC Kickoff Meeting. Request Meeting Invite here to join
Our 5 project contributors will present what they will work on between June and August 2026.
Here are the five accepted projects:

Polyglot P4TC: Python and Rust API Wrappers for Linux TC-based P4

Contributor: Attaullah Ansari, Birla Institute of Technology, Mesra

BMv2 packet trace support

Contributor: Yuao Ma, Huazhong University of Science and Technology

Improving The Traffic Manager of the P4Sim Switch

Contributor: Vineet Goel, Indian Institute of Technology Roorkee

Enhancing P4-SpecTec Usability: A Mechanized Specification for Nano-P4

Contributor: Haechan Kwon, Korea Advanced Institute of Science & Technology

Integrating P4 Based In Network Machine Learning Framework into P4Pi

Contributor: Yuzhong (WeiWei) Luo, University of Oxford

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P4 Developer Days – P4Check: a P4 Verification Tool
2026-06-25 08:00 - 09:00 (America/Vancouver)
Register to attend this P4 Developer Day webinar on June 25 at 8 am PT/11 am ET/5 pm CET
Slides (PDF) | Watch Recording
P4Check: a P4 Verification Tool

Abstract
We present P4Check, a scalable and practical one-stop shop for verifying data planes defined in P4. P4Check combines well-proven techniques, symbolic execution, big-step semantics and model checking with a novel high-level specification language into a tool to verify properties of stateful P4 programs at both the device and network levels. We present case studies showing property verification and bug detection for real-world P4 programs and conduct experiments to quantify the performance of P4Check compared to earlier works.
Speaker
Tommaso Pacciani is a PhD candidate in Multiscale Networked Systems (MNS) at the University of Amsterdam. His research focuses on applying formal methods and language design to enable the verification of programmable networks. His additional research interests include functional programming, effect systems, and debugging.

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