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X-WR-CALDESC:Events for P4 - Language Consortium
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DTSTART;TZID=UTC:20251001T090000
DTEND;TZID=UTC:20251001T090000
DTSTAMP:20260531T135115
CREATED:20250912T220316Z
LAST-MODIFIED:20251007T204714Z
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SUMMARY:P4 Developer Days - Enabling Portable and High-Performance SmartNIC Programs with Alkali
DESCRIPTION:Date: October 1\, 2025\nTime: 9:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nProgramming SmartNICs today is notoriously difficult. NICs from different vendors—or even different generations of the same vendor—exhibit significant variation in hardware parallelism\, memory hierarchies\, and interconnects. As a result\, porting programs across NICs is labor-intensive and requires extensive manual refactoring to meet performance expectations on each target. \nIn this presentation\, we will present the demo and design of Alkali\, a SmartNIC compilation framework that enables developers to write target-independent programs\, while the compiler automatically handles cross-NIC porting and performance tuning. Alkali achieves this by: (1) introducing a novel intermediate representation (IR) that supports building a reusable and extensible compiler across diverse NICs\, and (2) developing an optimization algorithm that automatically transforms and parallelizes programs based on the target NIC’s hardware characteristics. \nAlkali is built on the MLIR infrastructure and is fully open source (https://github.com/utnslab/Alkali). It currently supports four distinct NIC backends and continues to grow\, including future support for P4 as part of an effort to make SmartNIC programming more portable and productive. \nSpeakers\nJiaxin Lin is an incoming assistant professor at Cornell University. She received her Ph.D. from UT Austin in the summer of 2025. Her research aims to design innovative software and hardware for accelerated data center networks. She has received the Google and Meta PhD Fellowships in Computer Networking and was selected as an MIT EECS Rising Star in 2024. \n  \n \nZhiyuan Guo is a final-year PhD student at UC San Diego. His research focuses on co-designing datacenter systems and applications for resource disaggregation. He is actively extending the concept of disaggregation and cohesive design to various datacenter systems\, including remote memory\, networking accelerators\, and machine learning infrastructure. \n  \n 
URL:https://p4.org/event/p4-developer-days-enabling-portable-and-high-performance-smartnic-programs-with-alkali/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20251013T120000
DTEND;TZID=UTC:20251013T153000
DTSTAMP:20260531T135115
CREATED:20250912T220305Z
LAST-MODIFIED:20251119T000559Z
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SUMMARY:2025 P4 Workshop
DESCRIPTION:October 13th\, Noon – 3:30pm (in-person) – San Jose Convention Center\, Lower Level\, Room LL21B \nThe P4 Workshop event is an opportunity for the P4 ecosystem to share knowledge\, insights and experiences across the broader community and to facilitate collaboration. This year the workshop will be a hybrid event and feature both in-person and pre-recorded content. The in-person portion of the workshop will take place on October 13th in conjunction with the 2025 OCP Global Summit at the San Jose Convention Center in San Jose\, California. \nIn addition\, a P4 booth will be in the OCP Global Summit exhibit hall – make sure and stop by to talk with community members and learn about P4\, how its used and how to participate. Don’t miss a demo – “Gigaflow: Pipeline-Aware Caching in Virtual Switches with P4”. \nP4 Workshop Agenda (October 13th – noon – 3:30pm)\n\nWelcome – Fernando Ramos\nGeneral Chair 2025 P4 Workshop\nView Video | View Slides\nKEYNOTE: Mina Tahmasbi Arashloo – “High-Level and Target-Agnostic Transport Programs”\nAssistant Professor Canada Research Chair in Minimizing Human Error in Modern Networks Cheriton School of Computer Science\, University of Waterloo\nAbstract: Over the past two decades\, programming abstractios for packet processing have gained widespread adoption. These abstractions enable network operators to specify packet processing logic in high-level\, domain-specific languages that are independent of the underlying hardware architecture of packet processing nodes. This approach has unlocked numerous benefits\, including compiler-driven generation of efficient low-level implementations\, portability across diverse execution environments\, and automated testing and verification. Most existing abstractions\, however\, primarily focus on L2/L3 packet processing. In this talk\, we highlight the need for new programming abstractions that capture the complexities of network mechanisms essential for quality of service\, specifically transport protocols.\nView Video | View Slides\nVictor Rios – “DVaaS Detective: The Case of the Failing Tests”\nSoftware Engineer\, Google\nView Video | View Slides\nAnand Sridharan – “Cisco Silicon One: Unifying Network Forwarding with P4 Programmability”\nDistinguished Engineer\, Cisco\nView Video | View Slides\nBREAK\nTom Herbert – “Unifying P4 with eBPF and DPDK via XDP2”\nCEO\, XDPnet\nView Video | View Slides\nDebashis Chatterjee – “New Dawn of P4”\nSenior Director of Engineering\, Intel\nView Video | View Slides\nFabian Ruffy | Vladimir Gurevich – “XASM: A Foundation to Program the X2 with P4”\nSoftware Architect | Customer Solutions Architect\, XSight Labs\nView Video | View Slides\nKEYNOTE: Krishna Doddapaneni – “Using P4 NICs for Resilient Scale-out GPU Interconnect”\nCorporate Vice President\, AMD Pensando\nAbstract: AI transports demand hardware-based solution for low latency\, high throughput GPU interconnects. P4 seems a perfect match for demanding datapath transport enabled on programmable NIC for scale-out Ethernet fabrics. The industry is standardizing packet processing\, memory transfers\, message processing\, reliability\, multipathing\, etc. over the last few years. And we are at the beginning of building and standardizing these solutions. As network components multiplies — from cables and NICs to switches and transceivers\, failures become an inevitability. Chasing a myth of perfect reliability\, a more practical approach is to design a programmable network that anticipates and handles these failures gracefully. \n\nThis talk discusses how AMD leverages the P4 to build a robust solution that overcomes network failures\, implementing a multi-plane architecture and advanced failure-handling mechanisms. How P4 capabilities demonstrate network data plane programmability is a foundational requirement in today’s demanding and unforgiving AI environments.\nView Video | View Slides\n\nAndy Fingerhut – P4 Workshop Wrap-up\nPrincipal Engineer\, Cisco\n\nP4 Workshop Pre-Recorded Talks\n\nEric Campbell – “When P4 Isn’t Enough: Specifying The Control Interface”\nPostdoctoral Research Fellow\, UT Austin\nView Video | View Slides\nMehmet Emin Sahin – “High-Accuracy Updatable Bloom Filters for Robust Network Security in Programmable Networks”\nSystems and Network Administrator\, The Scientific and Technological Research Council of Turkiye\nView Video | View Slides\nMirek Walukiewicz – “Virtual IP Load Balancer using P4”\nPrincipal Engineer\, Altera\nView Video | View Slides\nPhani Suresh Paladugu – “Enabling Programmable Performance: Memory and Interconnect Innovation for AI-Centric Data Planes”\nExecutive Director – Product Management\, Synopsys\nView Video | View Slides\nJitesh Sreedharan Nambiar – “AI‑Enabled BOM Lifecycle for P4‑Programmable Infrastructure Reliability”\nBE Graduate\, Mumbai University\nView Video | View Slides\nMohammad Firas Sada – “Cross-Federated P4 Research Testbed for Wide-Area Programmable Networking Experiments”\nData Science Research Specialist\, San Diego Supercomputer Center\nView Video | View Slides\nShaan Nagy | Ali Kheradmand – “Automated Switch Validation with Path-Complete Testing at Scale”\nPhD Student\, UCSD | Senior Software Engineer\, Google\nView Video | View Slides\nAmith Gspn – “Real-Time Encrypted Traffic Classification with P4 and DPDK”\nGraduate Student Assistant and PhD Student\, University of South Carolina\nView Video | View Slides\n\nP4 Demo\nAdvay Singh | Ali Imran | Muhammad Shahbaz – “Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern SmartNICs”\nResearch Assistant | Graduate Student Research Assistant |  Assistant Professor EECS – Computer Science and Engineering\, University of Michigan\nView Demo \nGeneral Chair\nFernando Ramos\, University of Lisbon \nProgram Committee\nAmedeo Sapio\, NVIDIA\nAndy Fingerhut\, Cisco\nBen Pfaff\, Feldera\nChris Sommers\, KeySight\nGianni Antichi\, Politecnico di Milano & Queen Mary University of London\nJonathan DiLorenzo\, Google\nMario Baldi\, NVIDIA\nMuhammad Shahbaz\, University of Michigan\nVladimir Gurevich\, P4ica \nAll attendees and participants are expected to behave in accordance with professional standards and the Linux Foundation Events Code of Conduct – for more information\, see the full Code here.
URL:https://p4.org/event/2025-p4-workshop/
CATEGORIES:Events
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BEGIN:VEVENT
DTSTART;TZID=UTC:20251029T080000
DTEND;TZID=UTC:20251029T080000
DTSTAMP:20260531T135115
CREATED:20250912T220317Z
LAST-MODIFIED:20251104T173524Z
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SUMMARY:P4 Developer Days - P4sim: Protocol-Independent Packet Processors in ns-3
DESCRIPTION:P4 Developer Days webinar\, “P4sim: Protocol-Independent Packet Processors in ns-3”\nDate: October 29\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nNetwork simulation plays a crucial role in evaluating new architectures\, protocols\, and algorithms before deployment. While ns-3 is one of the most widely used discrete-event network simulators\, it lacks native support for programmable data plane behaviors described in P4. P4sim addresses this gap by integrating P4’s protocol-independent\, table-driven packet processing model into the ns-3 simulation framework. This talk introduces the architecture and capabilities of P4sim\, demonstrates how developers can prototype and test P4 programs in simulation environments\, and presents example use cases such as custom switching logic and in-band telemetry. Attendees will learn about the architecture and design of P4sim\, which supports P4 architectures like V1Model\, PSA\, and PNA. The talk highlights its integration with ns-3 and showcases practical use cases. P4sim enables early development and testing of P4 programs without hardware\, making it ideal for researchers and developers in programmable networking and simulation. \nSpeaker\n \nMingyu Ma is a Ph.D. researcher at Technische Universität Dresden\, Germany\, focusing on computer networks\, programmable data planes\, and simulation platforms. Mingyu has been actively involved in bridging the gap between research prototypes and real-world deployments\, with hands-on experience in P4\, ns-3 and traffic control. He regularly contributes to academic conferences and open-source communities related to network systems and simulation. \n  \n\n 
URL:https://p4.org/event/p4-developer-days-p4sim-protocol-independent-packet-processors-in-ns-3/
CATEGORIES:Events
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