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X-WR-CALNAME:P4 - Language Consortium
X-ORIGINAL-URL:https://p4.org
X-WR-CALDESC:Events for P4 - Language Consortium
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DTSTART:20240101T000000
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BEGIN:VEVENT
DTSTART;TZID=UTC:20250806T080000
DTEND;TZID=UTC:20250806T080000
DTSTAMP:20260531T052702
CREATED:20250912T220305Z
LAST-MODIFIED:20250915T225142Z
UID:10000129-1754467200-1754467200@p4.org
SUMMARY:P4 Developer Days - Gateway Use Case Architecture for Network Applications
DESCRIPTION:Date: August 6\, 2025Time: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES\nAbstract \nNetwork applications demand ever-increasing performance and flexibility. Mapping P4 programs directly to FPGA hardware offers a powerful solution\, but the design process can be complex. This presentation demonstrates a new toolchain for efficiently mapping P4 programs to Altera FPGAs\, significantly accelerating gateway applications. Presentation leads attendees through the complete flow\, from high-level P4 specification down to a fully synthesized FPGA design using a practical gateway example. Attendees will learn how this toolchain leverages p4 language capabilities to map the user application into FPGA. This session is ideal for network architects and hardware engineers seeking to leverage the power of P4 and FPGA acceleration for next-generation network applications. \nSpeaker\nPavel Benacek is Technical Lead at Altera with more than 12 years of experience in networking technology from research and industry. He is mainly working on hardware/software co-designs and high-level synthesis topics. He holds the Ph.D. at the Czech Technical University in Prague where he was working on theory of P4 language mapping to RTL design that can be synthesized to FPGA. \n 
URL:https://p4.org/event/p4-developer-days-gateway-use-case-architecture-for-network-applications/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20250820T090000
DTEND;TZID=UTC:20250820T090000
DTSTAMP:20260531T052702
CREATED:20250912T220316Z
LAST-MODIFIED:20250915T184729Z
UID:10000132-1755680400-1755680400@p4.org
SUMMARY:P4 Developer Days - Detecting Stragglers in Programmable Data Plane
DESCRIPTION:Date: August 20\, 2025Time 9:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nFlow scheduling mechanisms in modern datacenters aim to reduce flow completion time (FCT). However\, scheduling mechanisms that operate without prior knowledge\, such as PIAS\, or with imprecise flow information like QClimb\, can inadvertently introduce stragglers–packets within a flow that experience significantly higher queueing delays than others. These stragglers can lead to prolonged FCT\, undermining the goals of flow scheduling. In this talk\, we present StragFlow\, a data-plane tool for straggler detection. We implemented StragFlow in P4 using 740 lines of code. We evaluated StragFlow using real-world network traces and demonstrate that it can effectively detect stragglers across different scheduling schemes and various link conditions. Our results show that StragFlow can provide valuable insights into straggler distribution\, helping operators diagnose and mitigate flow scheduling issues to improve overall network performance. \nSpeaker\nRiz Maulana is a PhD Candidate within IRIS Cluster in the Department of Mathematics and Computer Science at Eindhoven University of Technology\, The Netherlands. His research interest includes programmable data plane\, probabilistic data structures\, and network monitoring. \n 
URL:https://p4.org/event/p4-developer-days-detecting-stragglers-in-programmable-data-plane/
CATEGORIES:Events
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