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X-WR-CALDESC:Events for P4 - Language Consortium
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DTSTART;TZID=UTC:20250604T080000
DTEND;TZID=UTC:20250604T080000
DTSTAMP:20260531T164439
CREATED:20250912T220259Z
LAST-MODIFIED:20250915T225237Z
UID:10000126-1749024000-1749024000@p4.org
SUMMARY:P4 Developer Days - Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern Smart NICs
DESCRIPTION:P4 Developer Days webinar\, “Pipeline-Aware Sub-Traversal Caching for Modern Smart NICs”\nDate: June 4\, 2025\nTime: 8:00am Pacific \nVIEW VIDEO \nVIEW SLIDES \nAbstract\nThe success of modern public/edge clouds hinges heavily on the performance of their end-host network stacks if they are to support the emerging and diverse tenants’ workloads (e.g.\, distributed training in the cloud to fast inference at the edge). Virtual Switches (vSwitches) are vital components of this stack\, providing a unified interface to enforce high-level policies on incoming packets and route them to physical interfaces\, containers\, or virtual machines. As performance demands escalate\, there has been a shift toward offloading vSwitch processing to SmartNICs to alleviate CPU load and improve efficiency. However\, existing solutions struggle to handle the growing flow rule space within the NIC\, leading to high miss rates and poor scalability. In this paper\, we introduce Gigaflow\, a novel caching system tailored for deployment on SmartNICs to accelerate vSwitch packet processing. Our core insight is that by harnessing the inherent pipeline-aware locality within programmable vSwitch pipelines—defining policies (e.g.\, L2\, L3\, and ACL) and their execution order (e.g.\, using P4 and OpenFlow)—we can create cache rules for shared segments (sub-traversals) within the pipeline\, rather than caching entire flows. These shared segments can be reused across multiple flows\, resulting in higher cache efficiency and greater rule-space coverage. Our evaluations—performed using Xilinx Alveo U250 data center accelerator running a Gigaflow pipeline written in P4—show that Gigaflow achieves up to a 51% improvement in cache hit rate (average 25% improvement) over traditional caching solutions (i.e.\, Megaflow)\, while capturing up to 450x more rule space within the limited memory of today’s SmartNICs—all while operating at line speed.  \nPublication Link : https://dl.acm.org/doi/10.1145/3676641.3716000 \nSpeaker\nAnnus Zulfiqar is a PhD candidate at the University of Michigan with Professor Muhammad Shahbaz. His research focuses on designing next generation hardware/software abstractions and architectures for emerging data center networking applications. Currently\, he is working on designing a scalable and efficient fast path for the Open vSwitch\, which is a widely used software switch in modern data centers. He is also working on ML for Systems where he has contributed to automatic generation of optimized data plane ML models and the development of scalable decision trees for programmable switches. \n 
URL:https://p4.org/event/p4-developer-days-gigaflow-pipeline-aware-sub-traversal-caching-for-modern-smart-nics/
CATEGORIES:Events
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DTSTART;TZID=UTC:20250611T080000
DTEND;TZID=UTC:20250611T080000
DTSTAMP:20260531T164439
CREATED:20250912T220304Z
LAST-MODIFIED:20250915T225203Z
UID:10000127-1749628800-1749628800@p4.org
SUMMARY:P4 GSoC 2025 Kickoff Meeting
DESCRIPTION:Learn about the projects hosted by the P4 Project in Google Summer of Code (GSoC) 2025. Each project will be presented by the contributor. \nAgenda \n\n\n\nIntroduction – Nate Foster\nGSoC proposal presentation + discussion:\n\n\n\n\n\n\n\n\nBMv2 With All Possible Output Packets – Xiyu Hao\nP4Sim Control Plane Enhancement – Vineet Goel\nP4MLIR: MLIR-based high-level IR for P4 compilers – Xiaomin Liu\nAccelerating OVS with Gigaflow: A Smart Cache for SmartNICs – Advay Singh\nSpliDT: Scaling Stateful Decision Tree Algorithms in P4 – Sankalp Jha\n\n\n\n\n\nVIEW VIDEO \nVIEW SLIDES
URL:https://p4.org/event/p4-gsoc-2025-kickoff-meeting/
CATEGORIES:Events
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