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X-WR-CALNAME:P4 - Language Consortium
X-ORIGINAL-URL:https://p4.org
X-WR-CALDESC:Events for P4 - Language Consortium
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TZID:UTC
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DTSTART:20230101T000000
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BEGIN:VEVENT
DTSTART;TZID=UTC:20241003T080000
DTEND;TZID=UTC:20241003T080000
DTSTAMP:20260531T233250
CREATED:20250912T220242Z
LAST-MODIFIED:20251001T192054Z
UID:10000122-1727942400-1727942400@p4.org
SUMMARY:2024 P4 Workshop
DESCRIPTION:The 2024 P4 Workshop took place October 3rd\, and was hosted and sponsored by Google. This in-person event took place at Google’s Moffett Park Campus in Sunnyvale\, California and offered an opportunity for the P4 ecosystem to share knowledge and experiences with the broader community and to facilitate collaboration. \nView individual videos and slides on-demand from the event below! Or\, view YouTube Playlist. \nInvited Talks\n\n\n  \n\n\n\n\n \nTitle\nVideo\nSlides\n\n\n\n\n\nWelcome\, State of P4 & 2024 Distinguished Contributor Award \nAndy Fingerhut\, Principal Engineer\, Intel\n\n\n\n\n\n\nKeynote – Navigating Internet Research with P4: Solutions for Performance and Security\nMaria Apostolaki\, Assistant Professor of Electrical and Computer Engineering\, Princeton University\n\n\n\n\n\n\nFireside Chat with Martin Casado\nMartin Casado\, General Partner\, Andreessen Horowitz\nNate Foster\, Professor Computer Science\, Cornell University\n\n\n\n\n\n\nP4 on Hardware: The Future\nKonstantin Weitz\, Staff Software Engineer\, Google (Moderator)\nVipin Jain\, Sr Fellow Engineer\, AMD\nAnjali Singhai Jain\, Network Architect\, Intel\n\n\n\n\n\nIn-Depth Talks\n\n\n  \n\n\n\n\n \nTitle\nVideo\n \nSlides\n\n\n\n\n\n\nPast\, Present and Future of P4\nDeb Chatterjee\, Sr Director Software Engineering\, Intel\n\n\n\n\n\n\nCompiler-assisted Kernel-based P4 Pipeline Offloading Using Intel IPU\nDeb Chatterjee\, Sr Director Software Engineering\, Intel\nNeha Singh\, Staff Software Engineer\, Intel\n\n\n\n\n\n\nTowards the Performant P4C\nAnton Korobeynikov\, Principal Software Engineer\, Compiler Development\, Access Softek Toolchains\n\n\n\n\n\n\nSupporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme\nBill Pontikakis\, Sr Research Associate\, Polytechnique Montréal\nFrançois-Raymond Boyer\, Professeur\, Polytechnique Montréal \n\n\n\n\n\n\n\nSONiC DASH on Intel IPU2100\nShweta Shrivastava\, Cloud Software Engineer\, Intel\nNamrata Limaye\, Director Software Engineering\, Intel \n\n\n\n\n\n\nInternals of the Intel Tofino Compiler\nGlen Gibb\, Compiler Engineer\, Intel\n\n\n\n\n\n\nP4-SpecTec – Mechanized Language Definition for P4\nJaehyun Lee\, Student\, KAIST\n\n\n\n\n\n\nCentralized Telemetry and Security Enforcement Using SONiC and P4\nShekher Bulusu\, Sr Manager Software Engineering\, GEICO\nPawan Ravi\, Sr Staff Engineer\, GEICO\nJames Choi\, Sr Engineering Manager\, GEICO\n\n\n\n\n\n\nModeling Hardware Blocks of Network ASICs using P4\nJean Tourrilhes\, Researcher\, HPE\n\n\n\n\n\n\nIn-Memory Key-Value Store Live Migration with NetMigrate\nZeying Zhu\, PhD Student\, University of Maryland\n\n\n\n\n\n\nP4-Based Automated Reasoning (P4-BAR) for the (Networking) Masses!\nSteffen Smolka\, Staff Software Engineer\, Google\nJonathan DiLorenzo\, Software Engineer\, Google\n\n\n\n\n\n\nScaling P4-Based Automated Reasoning (Performance and Coverage)\nAli Kheradmand\, Senior Software Engineer\, Google\nMeghana Sistla\, PhD Student\, University of Texas at Austin\n\n\n\n\n\n\nP4HIR: Toward Bridging P4C with MLIR\nBili Dong\, Software Engineer\, Google\n\n\n\n\n\nDemos\n\n  \n\n\n\n\n \nTitle\n \nAbstract\n\n\n \n\n\n\nSONiC DASH on Intel IPU2100\nNamrata Limaye\, Director Software Engineering\, Intel \n\n\n \n\n\n\nData Center Routing GEICO SDN Controller and GEICO SONiC Using P4\nSunil Kumar Rawookar\, Staff Engineer\, GEICO Tech\n\n\n \n\n\n\nOffload NAT and Routing onto Intel IPU Using P4-TC\nNeha Singh\, Staff Software Engineer\, Intel\n\n\n \n\n\n\nP4 IDE: An Integrated Development Environment for P4-based Data Plane Development\nNamrata Limaye\, Director Software Engineer\, Intel\n\n\n \n\n\nP4Docker: Simplifying P4 Switch Testbeds with Docker Integration \nLucas Trombeta\, PhD Candidate\, Federal University of ABC (UFABC)\n\n\n \n\n\n\nSupporting PTP-1588 in BMv2: A Proposed Ingress and Egress Timestamping Scheme\nBill Pontikakis\, Sr Research Associate\, Polytechnique Montréal\nFrançois-Raymond Boyer\, Professeur\, Polytechnique Montréal \n\n\n\n\nPoster\n\n  \n\n\n\n\n \nTitle\nAbstract\n\n\n\n\n\n\nBabel: The Tower So Far\nVictor Rios\, Software Engineer\, Google\n\n\n\n\nGeneral Chair – Nate Foster \nProgram Co-Chairs – Andy Fingerhut\, Muhammad Shahbaz \nProgram Committee\n– Jehandad Khan\, AMD\n– Ori Rottenstreich\, Technion\n– Vishal Shrivastav\, Purdue University\n– Gianni Antichi\, Politecnico di Milano and Queen Mary University of London\n– Ben Pfaff\, Feldera\n– Ajay Lotan Thakur\, Intel Corp\n– Victor Liu\, University of Michigan\n– Vladimir Gurevich\, P4ica\n– Tushar Swamy\, unaffiliated\n– Yiming Qiu\, University of Michigan\n– Amedeo Sapio\, Amazon Web Services\n– Lavanya Jose\, Google
URL:https://p4.org/event/2024-p4-workshop-postevent/
CATEGORIES:Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20241025T080000
DTEND;TZID=UTC:20241025T080000
DTSTAMP:20260531T233250
CREATED:20250912T220258Z
LAST-MODIFIED:20250915T225333Z
UID:10000123-1729843200-1729843200@p4.org
SUMMARY:Japan P4 Users Group
DESCRIPTION:The 2024 Japan P4 Users Group was hosted as a hybrid in-person and online event and included P4-related presentations and exhibits. View the agenda and resources. Talks were presented in Japanese and video can be accessed here.
URL:https://p4.org/event/japan-p4-users-group/
CATEGORIES:Events
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