ACM SIGCOMM is widely recognized as one of the best conferences — if not the best conference — in the field of computer networking. Many seminal papers were originally published at SIGCOMM, including the RMT paper, which provided the foundation for P4. This year’s conference featured a large number of P4-related papers, which hints at the growing enthusiasm for P4 in the research community.
Following are summaries of the P4-related papers that appeared at the conference:
This paper explores the issue of how best to write complex, stateful data plane programs. It develops a C-like language called Domino, and introduces the notion of a “packet transaction”: a sequential block of code that is executed atomically and in isolation from all other blocks of code. The authors identify primitives for implementing stateful programs efficiently in hardware and present a compiler pipeline that incorporates novel mechanisms based on software synthesis. To evaluate their design, the authors implement a variety of algorithms in Domino including load balancing, congestion control, active queue management, security, and network measurement.
This paper also proposes a language for expressing stateful data plane algorithms, but unlike Domino, it focuses on challenges related to programming an entire network, modeled as “one big virtual switch.” SNAP extends the local fragment of the NetKAT language with state variables that can be read and written by each packet. The SNAP compiler uses an intermediate representation based on FDDs and a constraint optimizer to generate data plane implementations that distribute state throughout the network while minimizing congestion.
This paper explores a new frontier in data plane programmability — the packet scheduler. The authors observe that many scheduling algorithms can be implemented using push-in first-out queues (PIFOs) and argue that PIFOs are feasible to implement in hardware, even when subject to the strict performance requirements inherent in operating at line rate on modern switches. The authors investigate the expressiveness of PIFOs and discuss implementations of a variety of algorithms from the literature including Least Slack-Time First, Stop-and-Go Queueing, Minimum Rate Guarantees, Priority-Based Schedling, and others. They demonstrate the feasibility of their approach by developing hardware design for a 64-port 10Gb/s switch that meets timing and adds modest overhead in terms of chip area.
This paper presents PISCES, an extension of OpenVSwitch (OVS) whose behavior can be customized using P4. PISCES takes as input a P4 source program that it compiles into C code that can be combined with a modified OVS to obtain a custom, high-performance switch. The key challenges involved in developing PISCES mostly relate to performance: how to keep the per-packet cost low on the fast path and ensure that not too many packets are diverted to the slow path, even in the presence of features such as arbitrary encapsulation and decapsulation of headers, complex control flow, and expensive checksum and validation operations. To address these challenges, PISCES incorporates a number of novel optimizations including inline editing of headers, incremental checksums, clever caching, and several others. The evaluation characterizes the effectiveness of these optimizations, both individually and together, as well as absolute performance on a variety of microbenchmarks.
This paper develops UnivMon, a new framework for network monitoring based on universal sketching. In UnivMon, the programmer specifies a monitoring task as a single program written using sketch primitives against a “one-big switch” virtual network. The system partitions the source program into code fragments that sample incoming traffic streams, populate local sketch counters on individual switches, and aggregate counters across switches to yield the final result. The data plane programs that implement sampling and tabulation are specified using P4. The authors evaluate their system on a suite of benchmarks including heavy-hitter detection, DDoS detection, change detection, entropy estimation, and others, and measure the accuracy
and memory usage of their solutions.
In addition to the presentations at the main conference, there were also a number of P4-related presentations at the NetPL workshop, which was held the day before SIGCOMM:
- Changhoon Kim from Barefoot Networks gave an invited talk on current trends and emerging directions for programmable data
- Han Wang from Cornell University presented a paper on a P4 to FPGA compiler.
- Rodrigo Fonseca from Brown University gave an invited talk on challenges related to the design of stateful primitives for programmable data planes.
This year SIGCOMM included a new industrial demo track. Half of the accepted demos presented systems related to P4:
- ONOS centralized control over a P4 programmable data plane, ON.Lab and Barefoot Networks;
- Tracking Any Packet’s Path and Latency via INT, Barefoot Networks;
- Xilinx P4 to NetFPGA SUME compilation flow, demonstrated for PERC congestion control algorithm experiments, Xilinx, Stanford, and MIT;
- VNF and µVNF chaining with in-band network telemetry for servers equipped with P4 / C programmable SmartNICs, Netronome.
There were two P4 related research track demos:
- High speed packet forwarding compiled from protocol independent data plane specifications, Eötvös Loránd University; Paper
- MACSAD: Multi-Architecture Compiler System for Abstract Dataplanes (aka Partnering P4 with ODP), Univ. of Campinas. Paper
In addition to the above, P4 was also discussed in the Q&A of other main conference papers. P4 and RMT were cited in several more papers and posters.
Lastly, for the second straight year, SIGCOMM featured a full-day P4 tutorial (Video), presented by Changhoon Kim and Jeongkeun “JK” Lee from Barefoot Networks. Over 30 people participated in the tutorial, which included presentations on the P4 language and associated tools, hands-on labs with exercises such as heavy-hitter detection, and a mini-workshop with talks on emerging and use cases and applications for P4.